Job Vacancies

Versatile Silicon Technologies, the 1^st Indonesia Fabless Semiconductor Company (www.vsilicon.com), is currently focusing their business in WiMax Baseband Chipset Design and Multinational Company Outsourcing. In order to support our development, we are looking for young Engineers to fulfill the following position:

1. RTL Engineer (3 persons)

2. Embedded Programming Engineer (5 persons)

3. OFDM Baseband Modeling Engineer (4 persons)

Qualifications:

1. RTL Engineer

* Has experience in RTL design and simulation using either VHDL or verilog

* Has experience in FPGA implementation

2. Embedded Programming Engineer

* Has experience in C programming

* Understand Operating System

* Preferable having experience in real-time programming

* Preferable having experience in driver programming

* Preferable understand IP packet programming

3. OFDM Baseband Modeling Engineer (4 persons)

* Good knowledge in Digital Communication Theory (channel coding, modulation, fading, OFDM etc..)

* Good knowledge in MATLAB programming

All candidates must also have following qualification:

* Good troubleshooting and debugging skill.

* Good communication skills in both oral and written (reporting)

* Has high commitment to meet project’s target and dateline

* Team work, matured and open personalities

* Degree in electrical engineering holders are welcome

If you meet above qualifications please send us your application letter, latest CV, recent photograph not later than April 30, 2008 to:

tadiono@vsilicon.com

Information on LEON3 Simulation

http://tech.groups.yahoo.com/group/leon_sparc/message/12106

Re: [leon_sparc] Running test program on leon in modelsim

You do not want to simulate a mkprom image in VHDL, trust me.
Even the smallest image will execute ~ 1,000,000 instructions
before entering main() in RAM. This is only ~ 30 ms on real
hardware at 50 MHz, but ~ 10 hours in VHDL (on a fast host).

You can easily see in TSIM how many instructions you will need:

sparc-elf-gcc -msoft-float hello.c -o hello.exe -lsmall
sparc-elf-mkprom hello.exe -nocomp -nomsg

tsim-leon3 prom.out
.
.
section: .text, addr: 0×0, size 34304 bytes
read 103 symbols
tsim> bre 0×40000000
breakpoint 1 at 0×40000000: .bdata
tsim> run
breakpoint 1 .bdata
tsim> per

Cycles : 1399497
Instructions : 906783
Overall CPI : 1.54

CPU performance (50.0 MHz) : 32.40 MOPS (32.40 MIPS, 0.00 MFLOPS)
Cache hit rate : 98.7 % (100.0 / 80.0)
AHB bandwidth utilisation : 33.7 % ( 0.4 / 33.3)
Simulated time : 27.99 ms
Processor utilisation : 100.00 %
Real-time performance : 11.86 %
Simulator performance : 3843.69 KIPS
Used time (sys + user) : 0.24 s

So even if we created the smallest possible binary using -lsmall
and fastest mkprom loading with -nomsg and -nocomp, you will need
to execute 906,783 instructions to get to RAM, and then maybe an
other 10,000 to get to main(). This is why the test bench in leon3
designs does NOT use mkprom, but a simple assembly reset sequence
and a pre-loaded RAM image…

Jiri.

sacliv wrote:
> Hey guys, I’m trying to load a test c program i wrote on the leon3 in
> the vhdl leon3 code and run it in modelsim to view the waveforms.
>
> I followed the bcc manual and did mkprom on my executable, and then i
> copied the .srec file to the testbench directory, and in the
> testbench.vhd, i changed the filename of the prom.srec to test.srec,
> which is my srec file.
>
> The test program is very simple and just prints out hello world, but
> in the modelsim simulation of the leon3, i’m watching the pc and
> instructions of the leon3 core, but i can’t seem to get to my test
> program.
>
> Does anyone know either how long i have to simulate it until before i
> get to main() in my test program? Or if i’m doing it wrong, what’s the
> correct procedure? Thanks!

================================================================================================
http://tech.groups.yahoo.com/group/leon_sparc/message/12108

Re: [leon_sparc] Re: Running test program on leon in modelsim

See how the test bench is compiled by doing ‘make soft’ in the
template design directory. The final command will be:

sparc-elf-gcc -I../../software/leon3 -O2 -g -msoft-float systest.c -L./
lib3tests.a -o systest.exe
sparc-elf-objcopy -O srec systest.exe sram.srec

You can do pretty much the same using your own application:

sparc-elf-gcc -O2 -g -msoft-float myapp.c -o myapp.exe
sparc-elf-objcopy -O srec myapp.exe sram.srec

And make sure you understand how to use the ‘volatile’ keyword
in C if you intend to do any memory tests or similar …

Jiri.

sacliv wrote:
> Wow that’s good to know. So is there a way to easily simulate my test
> code using the leon3 VHDL code?

================================================================================================

http://tech.groups.yahoo.com/group/leon_sparc/message/12114

Re: [leon_sparc] Re: Running test program on leon in modelsim

You can run your code from PROM for fastest run-time. Copy prom.S
from software/leon3 to you local template design, and do ‘make soft’.
Then, add your instructions just before the code jumps to RAM at
the end of the file:

set RAMSTART, %g1
<–insert here
jmp %g1
nop

Do a ‘make soft’ again, and restart simulation. Note that you can
get assembly output from the simulation by setting the disas generic
to 1 (or start modelsim with -gdisas=1) .

Jiri.

================================================================================================

http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=92&Itemid=66

How do I put the content of a file “as is” into the .data section (or somewhere else into memory)?
You can add a binary file to an existing elf file with objcopy, by adding a new section and fill it with the desired content:

sparc-elf-objcopy –add-section .myelfsection=file.bin –change-section-address .myelfsection=0×00001000

–set-section-flags .myelfsection=alloc,contents,load,data file.exe

The example above adds the file ‘file.bin’ to the elf file ‘file.exe’ at address 0×1000. Note that this is done after linking.

================================================================================================

Design Examples For Altera Terasic DE2 Board

Here is the project :

http://www.geocities.com/akhmadm/hdl_design/DE2_sunset.zip

The design is very simple, only viewing a image (sunset) that saved in 3 ROM.
Use Matlab to convert the image to text files.
Use tb_de2.v to covert text files to Altera mif file (click the the de2.mpf to open Modelsim, then execute script compile.do.
Change the mif file to hex file using quartus editor or quartus tool (open mif file then save as hex file).
You can use the altera_rom function for another design.

Using DDD and GRMON

Open GRMON in a terminal (shell).

grmon-eval -nosram -uart /dev/ttyUSB0 -u -nb

GRMON LEON debug monitor v1.1.27b (evaluation version)

Copyright (C) 2004,2005 Gaisler Research – all rights reserved.
For latest updates, go to http://www.gaisler.com/
Comments or bug-reports to support@gaisler.com

This evaluation version will expire on 28/6/2008
using port /dev/ttyUSB0 @ 115200 baud

GRLIB build version: 2710

initialising ……….
detected frequency: 50 MHz

Component Vendor
LEON3 SPARC V8 Processor Gaisler Research
AHB Debug UART Gaisler Research
AHB Debug JTAG TAP Gaisler Research
LEON2 Memory Controller European Space Agency
AHB/APB Bridge Gaisler Research
LEON3 Debug Support Unit Gaisler Research
Generic APB UART Gaisler Research
Multi-processor Interrupt Ctrl Gaisler Research
Modular Timer Unit Gaisler Research
General purpose I/O port Gaisler Research

Use command ‘info sys’ to print a detailed report of attached cores

grlib> gdb

you will get a message:

gdb interface: using port 2222

On the other terminal (shell), run the DDD using the following command:

target extended-remote localhost:2222

The grmon shell will generate a message:

connected to port 2222

In the DDD, open program systes2.exe
On the DDD, gdb prompt, type “lo systest2.exe” , then run.

GNU DDD 3.3.11 (i386-suse-linux-gnu), by Dorothea Lütkehaus and Andreas Zeller.
Copyright © 1995-1999 Technische Universität Braunschweig, Germany.
Copyright © 1999-2001 Universität Passau, Germany.
Copyright © 2001 Universität des Saarlandes, Germany.
Copyright © 2001-2004 Free Software Foundation, Inc.
(gdb) file /home/mul/grlib-gpl-1.0.17-b2710/designs/leon3-altera-ep1s40/systest2.exe
(gdb) lo systest2.exe
You can’t do that when your target is `exec’
(gdb) target extended-remote localhost:2222
start () at ../../../../../newlib-1.13.0/libgloss/sparc_leon/locore_mvt.S:58
in ../../../../../newlib-1.13.0/libgloss/sparc_leon/locore_mvt.S
Current language: auto; currently asm
(gdb) lo systest2.exe
Loading section .text, size 0×10db0 lma 0×40000000
Loading section .data, size 0×7e14 lma 0×40011000
Start address 0×40000000, load size 101316
Transfer rate: 42659 bits/sec, 278 bytes/write.
(gdb) run

Starting test …
LEON3 V8 Processor
register file
multiplier
radix-2 divider
cache system
memory management unit
Interrupt Controller
Modular Timer unit
timer 0
timer 1
chain-mode
UART
sub-test

Tested ended

Program exited normally.
(gdb)

Using GRMON with USB-Serial Device

The Command :

grmon-eval -nosram /dev/ttyUSB0

or

grmon-eval -nosram /dev/ttyUSB1

Verilog task for loading text file to registers

CODE :

integer data [255:0];

task read_file;
input integer i_infile;
input integer numdata;
input integer indeks_init;
input reg [7:0] file_type;
input display_testvector;

integer indeks;
integer kolom,baris;
integer i_c,i_r,i;

reg file_opened,file_closed;

begin
//$display("============= %s ======================",file_type);
file_opened = 1'b0;
file_closed = 1'b0;
i_c = 0;
i_r = 0;
indeks = indeks_init;

for(i=0; i<(numdata); i=i+1)
begin
data[i] = 0;
end

if (i_infile ==0) // If error opening file
begin
$display("File input not found !!!!!!!");
disable file_input_block; // Just quit
end
else
begin
file_opened = 1'b1;
end

if (~file_closed & file_opened)
begin
i_c = $fgetc(i_infile);
//$display("%8x", i_c);
while (i_c != `EOF)//
begin
if (i_c == "/")
begin
i_r = $ungetc(i_c, i_infile);
//$display("COMMENT");
i_c = $fgets(line, i_infile); // Read the comment
if (display_testvector == 1'b1)
begin
$display("%s", line);
end
end
else
begin

i_r = $ungetc(i_c, i_infile); // PuSH char back
if(file_type=="h") begin
i_c = $fscanf(i_infile,"%x",data[indeks]);
end else begin
i_c = $fscanf(i_infile,"%d",data[indeks]);
end

if (display_testvector == 1'b1)
begin
$display(" data[%8d] = %8x",indeks,data[indeks]);
end
indeks = indeks + 1;
end

i_c = $fgetc(i_infile);
//$display("%8x", i_c);
if(indeks==numdata)
begin
i_c = `EOF;
end

end
$fclose(i_infile);
file_closed = 1'b1;
end
end
endtask

HOW TO USE THE TASK :

1. Add task read_file in your verilog tesbench.
2. Call the task, example:


integer i_infile;

initial
begin : file_input_block
starter = 1'b0;
//----------------------------------------
//read file test vector test_in.txt
//----------------------------------------
i_infile1 = $fopen("./testvector/test_in.txt", "r");
read_file(i_infile1,256,1,"d",0);
for(i=0; i<(256); i=i+1) begin
regfile[i] = data[i];
end

//starting the test
starter = 1'b1;

dut dut_inst (
.clk (clk)
,.addr (addr)
,.datain (regfile[addr])
);

end


Using GRMON with Altera ByteBlaster

The command is :

grmon-eval.exe -u -altjtag

Implementation of LEON3 on Nios Stratix EP1S40F780C5 use the following command:

grmon-eval.exe -altjtag -nosram

The linux image downloaded to sdram at 0×40000000 and the console connected to AHB uart (J19). The debug uart (j27) not used. If -nosram not used then sdram address will be indentified at 0×60000000.

Divider Architecture

Parallel Divider Architecture :

Here is the example Verilog divider code : divider.pdf

Serial Divider Architecture :

(click the image to enlarge)
divider.pdf

ModelSim Script for Altera Simulation

transcript on
if ![file isdirectory verilog_libs] {
file mkdir verilog_libs
}

vlib verilog_libs/stratixii_ver
vmap stratixii_ver verilog_libs/stratixii_ver
vlog -work stratixii_ver c:/altera/quartus60/eda/sim_lib/stratixii_atoms.v

vlib verilog_libs/lpm_ver
vmap lpm_ver verilog_libs/lpm_ver
vlog -work lpm_ver c:/altera/quartus60/eda/sim_lib/220model.v

vlib verilog_libs/altera_ver
vmap altera_ver verilog_libs/altera_ver
vlog -work altera_ver c:/altera/quartus60/eda/sim_lib/altera_primitives.v

vlib verilog_libs/altera_mf_ver
vmap altera_mf_ver verilog_libs/altera_mf_ver
vlog -work altera_mf_ver c:/altera/quartus60/eda/sim_lib/altera_mf.v

vlib verilog_libs/sgate_ver
vmap sgate_ver verilog_libs/sgate_ver
vlog -work sgate_ver c:/altera/quartus60/eda/sim_lib/sgate.v

if {[file exists rtl_work]} {
vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

vlog -work rtl_work ./rtl/cordic-mul/add_sub.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/cordic-mul/unsign.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/cordic-mul/dff_acc.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/cordic-mul/dffen_acc.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/cordic-mul/angle_rom.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/cordic-mul/iterator_ctrl.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/cordic-mul/iterator.v +incdir+./rtl +define+SIM

vlog -work rtl_work ./rtl/negator.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/extender.v +incdir+./rtl +define+SIM
vlog -work rtl_work -L lpm_ver ./fpga/rtl/add_sub19.v
vlog -work rtl_work -L lpm_ver ./fpga/rtl/add_sub22.v
vlog -work rtl_work -L altera_mf_ver ./fpga/rtl/angle1.v
vlog -work rtl_work ./rtl/cordic-mul-2/iterator_ctrl1.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/cordic-mul-2/iterator_ctrl1p.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/cordic-mul-2/iterator1.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/cordic-mul-2/iterator1p.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/cordic-mul-2/cordic_mul.v +incdir+./rtl +define+SIM

vlog -work rtl_work ./rtl/parallel-divider/casblock32p.v +incdir+./rtl +incdir+./rtl/parallel-divider +define+SIM
vlog -work rtl_work ./rtl/parallel-divider/divider32.v +incdir+./rtl +incdir+./rtl/parallel-divider +define+SIM

vlog -work rtl_work ./rtl/parallel-divider/casblockparameterized.v +incdir+./rtl +incdir+./rtl/parallel-divider +define+SIM
vlog -work rtl_work ./rtl/parallel-divider/divider_parameterized.v +incdir+./rtl +incdir+./rtl/parallel-divider +define+SIM

vlog -work rtl_work ./rtl/pipe_mxn.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/pipe_mx1.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/hls.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/est_ctrl.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/estimator_top.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/registers.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/eq_div.v +incdir+./rtl +define+SIM
vlog -work rtl_work -L lpm_ver ./fpga/rtl/divider32sign_1clk.v
vlog -work rtl_work -L lpm_ver ./rtl/eq_divp1.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/eq_div_lpm.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/averager.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/r_proc.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/theta_proc.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/ram_sel.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/data_sel.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/theta_neg.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/eq_ctrl.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/ram_output.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/equalizer.v +incdir+./rtl +define+SIM

vlog -work rtl_work ./testbench/functions_lib.v +incdir+./testbench +incdir+./rtl
vlog -work rtl_work ./testbench/task_lib.v +incdir+./testbench +incdir+./rtl
vlog -work rtl_work ./testbench/tb_equalizer.v +incdir+./testbench +incdir+./rtl

vsim -t 1ps -L rtl_work -L lpm_ver -L altera_mf_ver tb_equalizer

Passing parameter value from do file to verilog

Here is part of tesbench for divider exhaustive test.


initial begin // Exhaustive patterns
#delay_for_exhaustive_patterns
word_dividend = `START_NUM;
while (word_dividend <= `END_NUM)
begin
word_divisor = 1;
while (word_divisor <= `MAX_DIVISOR) begin
#0 Start = 0;
#start_offset Start = 1;
#start_duration Start = 0;
@ (posedge Ready)
#0;
word_divisor = word_divisor + 1;
end // divisor pattern
word_dividend = word_dividend + 1;
end // dividend pattern
$stop;
end


If you want test in an automatic multiple test with separate log file, then we need pass some paramater value and some file name from do file to verilog.

Here is the example of the do file :

vlog ./rtl/Dividers/Divider_STG_0.v +incdir+./rtl
#vlog ./rtl/Dividers/Divider_STG_1.v +incdir+./rtl
#vlog ./rtl/Dividers/Divider_STG_0_sub.v +incdir+./rtl
vlog ./rtl/Dividers/Divider_RR_STG.v +incdir+./rtl/Dividers

exec start_time.exe
set ontest 1
set numtest 1

while {$ontest} {
set out [open namefile.txt w]
scan $numtest "%4x" filename
puts $out [format "test%4x.txt" $filename ]
close $out
vlog ./rtl/Dividers/t_Divider_RR_STG.v +incdir+./rtl/Dividers +define+START_NUM=$numtest +define+END_NUM=8'hFF +define+namefile=$numtest
vsim test_Divider_RR_STG
run -all
incr numtest
if {$numtest == 256} {set ontest 0}
}

exec end_time.exe
exec playing_sound.exe

the comand :

set out [open namefile.txt w]
scan $numtest "%4x" filename
puts $out [format "test%4x.txt" $filename ]
close $out



convert numtest to string and save it in namefile.txt. Verilog tesbench then read namefile.txt and use the contain of namefile.txt as log file name. Here is the verilog code :


initial

begin : log_file

dumpfile1 = $fopen("namefile.txt", "r");
i_c = $fgets(indeks, dumpfile1);
$display("hallo%s",indeks);
$fclose(dumpfile1);

end

always @ (posedge quotient_error or posedge rem_error or posedge reset) begin
if(reset) begin
cnt_quot_error <= 16'd0;
cnt_rem_error <= 16'd0;
end
else if(quotient_error | rem_error) begin
dumpfile2 = $fopen(indeks, "w");
if(quotient_error) begin
cnt_quot_error <= cnt_quot_error + 16'd1;
$fdisplay(dumpfile2,"quot= %14x %14x exp_quot error ",quotient,expected_quotient,cnt_quot_error);
end
if(rem_error) begin
cnt_rem_error <= cnt_rem_error + 16'd1;
$fdisplay(dumpfile2,"rem= %14x %14x exp_rem error",remainder,expected_remainder,cnt_rem_error);
end
$fclose(dumpfile2);
end

end