Synopsys TetraMAX® ATPG script

After you create the reg_bank.v (with scan insertion), You can use Synopsys TetraMAX® ATPG to test it.
Here is the script for Synopsys TetraMAX® ATPG, orion_tm_reg_bank.tm :


read netlist -delete
#Read the gate level design (counter4_net.v) and the technology library (umc18all.v).
read netlist /home/mul/data/TSMC_CL018G/StandCell/aci/sc/verilog/tsmc18.v
read netlist ./netlist/reg_bank.v
#Build the schematic of the design
run build_model reg_bank
#The schematic can be shown by clicking SHOW->ALL
# Add scan clock port information
add clocks 0 clk -shift -timing 1000 100 200 300
# Add scan_in and scan_out port information
add scan chain c0 sc_in sc_out
#Activate scan enable signal
add scan enables 1 sc_en
#Perform Design Rule Check
drc
test
#Add faults
set faults -model stuck
add faults -all
#Run test pattern generation
run atpg
#run report
report violations -all >> ./report/reg_bank_violation.rpt
report faults -all >> ./report/reg_bank_fault.rpt
report patterns -all >> ./report/reg_bank_patterns.rpt
#Compress pattern
run pattern_compression 1 -min_eliminated_pats 0 -max_useless_passes off -verbose
#Write pattern as simpatter.v
write patterns simpattern.v -replace -internal -format verilog_single_file -parallel 0


To run design analyzer in command prompt you can use the following command :

tmax -f orion_tm_reg_bank.tm

or

tmax32 -f orion_tm_reg_bank.tm