Using Conv_Integer for behavioral memory design in VHDL
Posted by mulyanto on May 31, 2007
If you plan your design will be implemented in FPGA, you have use the syncronous memory. In the simulation phase, you can use the generic behavioral memory design, but in the fpga implementation phase you have change the generic behavioral memory into the vendor memory(Xilinx Core or Altera Megafunction).
Here is the generic behavioral memory code :


ropi said
thx maaan, helped
Damien said
Thank you very much! Very helpful!