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Using Conv_Integer for behavioral memory design in VHDL

Posted by mulyanto on May 31, 2007

If you plan your design will be implemented in FPGA, you have use the syncronous memory. In the simulation phase, you can use the generic behavioral memory design, but in the fpga implementation phase you have change the generic behavioral memory into the vendor memory(Xilinx Core or Altera Megafunction).

Here is the generic behavioral memory code :

sincram1.jpg

2 Responses to “Using Conv_Integer for behavioral memory design in VHDL”

  1. ropi said

    thx maaan, helped

  2. Damien said

    Thank you very much! Very helpful!

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