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Design Examples For Xilinx University Program XUP Virtex-II Pro Development System : RS232 Interface

Posted by mulyanto on June 22, 2007

13 Responses to “Design Examples For Xilinx University Program XUP Virtex-II Pro Development System : RS232 Interface”

  1. lamjed said

    Very Kind Sir.

  2. pkab said

    Dear Mulyanto,

    Which ISE software do you use when developing using XUPV2P?
    Thank you very much in advance.

    best regards,
    suryadi

  3. mulyanto said

    @Pkab
    It is ISE 8.2i. You can find it in rs232_svga_summary.html.
    This example may not working on another version ISE :)

    Thank You.

  4. Lina said

    I need to design a VHDL code for a simple UART and download it to Spartan 3 board.
    I am trying to send a serial data via RS232 to the Spartan 3 board.
    I’ve asked my lecturer regarding this problem but she also have no idea how to interface via RS232.
    Does it have any specific source code to interface with RS232? If it does, can you email me the source code? May be it can give me an idea to solve the problem.
    Hope to hear the good news from you soon.

    Thanks in advance.
    Lina

  5. Lina said

    @Lina
    Have you download the file? :

    http://www.geocities.com/akhmadm/hdl_design/xup_rs232_vga.zip

    Have you read the files?

    I’ve download that file. I’ll try it.
    Thanks.

  6. Lina said

    How do we set the clock frequency to get the baud rate divisor? From the file that I’d downloaded, there is a VHDL code for RS232. Is it the specific VHDL code for the RS232? One more question. How can I get the data from PC via RS232? Just connect the RS232 cable and run the program or what?

    ____________________________________________________________________
    Mulyanto :
    1. Use PLL or DCIM set the clock frequency;
    2. The VHDL code is a rs 232 interface. Its receive the sequence of 1 bit serial data from rs 232 port using serial protocol, resulting 8 bit data at final. The code also send serial data to rs 232 port from 8 bit data.
    3. How can I get the data from PC via RS232?
    a. Use the Hyperterminal or other software or write a c code.
    b. Make the vhdl to receive data and display/store the received data.

  7. Lina said

    3. How can I get the data from PC via RS232?
    a. Use the Hyperterminal or other software or write a c code.
    b. Make the vhdl to receive data and display/store the received data.
    ____________________________________________________________________

    Sorry. Forgot to tell you. My data is from Matlab. I’ve designed PCM model using Matlab to digitize my analog input source. The output from the Matlab will be received by the RS232. Can I just connect the cable without using the hyperterminal or other software?

    —————————————————————————————————————–
    Mulyanto :

    I don’t know. Maybe the other software is Matlab :) .

  8. Mona said

    Hello Mulyanto,

    I hope this message finds you well.
    I downloaded your Sunset project. I compiled it and then ran it, but it doesn’t work.
    But when I run it without compiling it works. why is that? Is the code written correct? Please help.
    Many Thanks

    ————————————————————————————————
    Mulyanto :

    Maybe because you use different ISE. I was using ISE 8.2i. You can find it in rs232_svga_summary.html.
    This example may not working on another version ISE :)

    Thank You.

  9. NITIN GUPTA said

    I want to work on active filters, and wants to implement the model on Spartan3A DSPor Virtex-5 board.
    My inputs are in form of voltage and current and after processing by FPGA processor output will be 6 or 12 firing pulse which will be send to IGBT inverter gate circuit.
    Here I am not getting that how input and output will be configured to the Board. In system generator there is no option for PI controller or fuzzy controller, it means that if we want to make some controller then what is the procedure for that. Pl tell me about this.

    1. Xilinx device XC3SD1800A-4FGG676C Spartan 3A DSP FPGA
    2. Virtex -5 FPGA Evaluation Platform (ML505) XC5VLX50T-FFG1136

    As I am at the entry level in FPGA kits and wants to implement some single or three phase active filter topology. Here I am attaching the basic scheme of active filter.

    1. Line Current and Voltage will be sensed by some sensors, here I am using LEM sensors.
    2. These signal will be send to FPGA kits via some interface such as ADC or DAC.
    3. Again controller will generate switching signal which again will be send to some IGBT based inverter circuits. But the main point is how to design a controller in system generator as there is no sufficient block for that.

    Sir, I want to use System Generator here , but I am not understanding that VHDL will be required here or not.

    ——————————————————————————-
    Mulyanto :

    You can make a small lookup table (or rom) with finite state machine design. This small design act a signal generator that a model of ADC (ADC generated signals from LEM sensor).

    So you have to model signals generated by ADC. Then make HDL code for the model. The design should be small, you can adjust the size of lookup table (or rom).

  10. Mona said

    Hi Mulyanto,
    I hope this message finds you well.

    Could you please check this Matlab file for me. I just want a gray image in text format.

    ——————————————
    %% process a bitmap into a MIF file
    %% read the image and show it

    name = ‘anouv1′;
    img = imread(strcat(name,’.gif’));
    g = im2double(img);
    g = g/max(max(g));
    rgb = cat(3,g,g,g);
    imshow(rgb);

    %% insert into 640 x 480 region

    out = ones(480,640);
    out(10+(1:460),90+(1:460)) = img;
    imshow(out);

    %% print pixels

    x = out’;
    x = uint8(x(:));
    fid = fopen(strcat(name,’.txt’),’w');
    fprintf(fid,’%X ‘,x);
    fclose(fid);

    —————————————————————————————————————
    Mulyanto :

    Forgive me, I can’t check your matlab code. I’m using linux without
    matlab and fpga.

    Maybe you can use rgb2gray

    http://www.mathworks.com/access/helpdesk/help/toolbox/images/rgb2gray.html

    rgb2gray – Convert RGB image or colormap to grayscale
    Syntax

    I = rgb2gray(RGB)
    newmap = rgb2gray(map)
    Description

    I = rgb2gray(RGB) converts the truecolor image RGB to the grayscale
    intensity image I. rgb2gray converts RGB images to grayscale by
    eliminating the hue and saturation information while retaining the
    luminance.

    newmap = rgb2gray(map) returns a grayscale colormap equivalent to map.

    Note A grayscale image is also called a gray-scale, gray
    scale, or gray-level image.

    Class Support

    If the input is an RGB image, it can be of class uint8, uint16,
    single, or double. The output image I is of the same class as the
    input image. If the input is a colormap, the input and output
    colormaps are both of class double.
    Examples

    Convert an RGB image to a grayscale image.

    I = imread(‘board.tif’);
    J = rgb2gray(I);
    figure, imshow(I), figure, imshow(J);

    Convert the colormap to a grayscale colormap.

    [X,map] = imread(‘trees.tif’);
    gmap = rgb2gray(map);
    figure, imshow(X,map), figure, imshow(X,gmap);

    Algorithm

    rgb2gray converts RGB values to grayscale values by forming a weighted
    sum of the R, G, and B components:

    0.2989 * R + 0.5870 * G + 0.1140 * B

    Note that these are the same weights used by the rgb2ntsc function to
    compute the Y component.
    See Also

    ind2gray, mat2gray, ntsc2rgb, rgb2ind, rgb2ntsc

  11. Sruthi Manchala said

    Hi

    Hope this messg finds u in good health. I need to send configuration bit file onto FPAA through RS232 port of FPGA. Please help me with code related to that as I’m a beginner

    Thanks a lot

    • mulyanto said

      There is no such short cut to learn RS322 in FPGA. You have the code, you have the book. All you have to do is learn and experiment.

      Thanks.

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