Making SIMPRIM Library for Modelsim
Posted by mulyanto on June 29, 2007
In order to run the Xilinx post-layout model simulation properly, your Modelsim must have a SIMPRIM library. If your Modelsim does not have it, follow the instruction below:
1. Open Modelsim
2. Change directory to C:\Modeltech_6.0
3. Run the script below:
set xilinx_src “C:/Xilinx/verilog/src”
vlib simprims_ver
vlog -work simprims_ver $xilinx_src/glbl.v
vlog -work simprims_ver $xilinx_src/simprims/X_ZERO.v
vlog -work simprims_ver $xilinx_src/simprims/X_AFIFO36_INTERNAL.v
vlog -work simprims_ver $xilinx_src/simprims/X_AND2.v
vlog -work simprims_ver $xilinx_src/simprims/X_AND3.v
vlog -work simprims_ver $xilinx_src/simprims/X_AND4.v
vlog -work simprims_ver $xilinx_src/simprims/X_AND5.v
vlog -work simprims_ver $xilinx_src/simprims/X_AND6.v
vlog -work simprims_ver $xilinx_src/simprims/X_AND7.v
vlog -work simprims_ver $xilinx_src/simprims/X_AND8.v
vlog -work simprims_ver $xilinx_src/simprims/X_AND9.v
vlog -work simprims_ver $xilinx_src/simprims/X_AND16.v
vlog -work simprims_ver $xilinx_src/simprims/X_AND32.v
vlog -work simprims_ver $xilinx_src/simprims/X_ARAMB36_INTERNAL.v
vlog -work simprims_ver $xilinx_src/simprims/X_BPAD.v
vlog -work simprims_ver $xilinx_src/simprims/X_BSCAN_FPGACORE.v
vlog -work simprims_ver $xilinx_src/simprims/X_BSCAN_SPARTAN2.v
vlog -work simprims_ver $xilinx_src/simprims/X_BSCAN_SPARTAN3.v
vlog -work simprims_ver $xilinx_src/simprims/X_BSCAN_VIRTEX2.v
vlog -work simprims_ver $xilinx_src/simprims/X_BSCAN_VIRTEX4.v
vlog -work simprims_ver $xilinx_src/simprims/X_BSCAN_VIRTEX5.v
vlog -work simprims_ver $xilinx_src/simprims/X_BSCAN_VIRTEX.v
vlog -work simprims_ver $xilinx_src/simprims/X_BUF.v
vlog -work simprims_ver $xilinx_src/simprims/X_BUFGCTRL.v
vlog -work simprims_ver $xilinx_src/simprims/X_BUFGMUX.v
vlog -work simprims_ver $xilinx_src/simprims/X_BUFGMUX_1.v
vlog -work simprims_ver $xilinx_src/simprims/X_BUFR.v
vlog -work simprims_ver $xilinx_src/simprims/X_CARRY4.v
vlog -work simprims_ver $xilinx_src/simprims/X_CKBUF.v
vlog -work simprims_ver $xilinx_src/simprims/X_CLK_DIV.v
vlog -work simprims_ver $xilinx_src/simprims/X_CLKDLL.v
vlog -work simprims_ver $xilinx_src/simprims/X_CLKDLLE.v
vlog -work simprims_ver $xilinx_src/simprims/X_CRC32.v
vlog -work simprims_ver $xilinx_src/simprims/X_CRC64.v
vlog -work simprims_ver $xilinx_src/simprims/X_DCM.v
vlog -work simprims_ver $xilinx_src/simprims/X_DCM_ADV.v
vlog -work simprims_ver $xilinx_src/simprims/X_DCM_SP.v
vlog -work simprims_ver $xilinx_src/simprims/X_DSP48.v
vlog -work simprims_ver $xilinx_src/simprims/X_DSP48E.v
vlog -work simprims_ver $xilinx_src/simprims/X_EMAC.v
vlog -work simprims_ver $xilinx_src/simprims/X_FDD.v
vlog -work simprims_ver $xilinx_src/simprims/X_FDDRCPE.v
vlog -work simprims_ver $xilinx_src/simprims/X_FDDRRSE.v
vlog -work simprims_ver $xilinx_src/simprims/X_FF.v
vlog -work simprims_ver $xilinx_src/simprims/X_FIFO16.v
vlog -work simprims_ver $xilinx_src/simprims/X_FIFO18.v
vlog -work simprims_ver $xilinx_src/simprims/X_FIFO18_36.v
vlog -work simprims_ver $xilinx_src/simprims/X_FIFO36_72_EXP.v
vlog -work simprims_ver $xilinx_src/simprims/X_FIFO36_EXP.v
vlog -work simprims_ver $xilinx_src/simprims/X_GT10.v
vlog -work simprims_ver $xilinx_src/simprims/X_GT11.v
vlog -work simprims_ver $xilinx_src/simprims/X_GT11CLK.v
vlog -work simprims_ver $xilinx_src/simprims/X_GT.v
vlog -work simprims_ver $xilinx_src/simprims/X_IBUFDS.v
vlog -work simprims_ver $xilinx_src/simprims/X_IDDR2.v
vlog -work simprims_ver $xilinx_src/simprims/X_IDDR.v
vlog -work simprims_ver $xilinx_src/simprims/X_IDELAY.v
vlog -work simprims_ver $xilinx_src/simprims/X_IDELAYCTRL.v
vlog -work simprims_ver $xilinx_src/simprims/X_INV.v
vlog -work simprims_ver $xilinx_src/simprims/X_IODELAY.v
vlog -work simprims_ver $xilinx_src/simprims/X_IPAD.v
vlog -work simprims_ver $xilinx_src/simprims/X_ISERDES.v
vlog -work simprims_ver $xilinx_src/simprims/X_ISERDES_NODELAY.v
vlog -work simprims_ver $xilinx_src/simprims/X_KEEPER.v
vlog -work simprims_ver $xilinx_src/simprims/X_LATCH.v
vlog -work simprims_ver $xilinx_src/simprims/X_LATCHE.v
vlog -work simprims_ver $xilinx_src/simprims/X_LUT2.v
vlog -work simprims_ver $xilinx_src/simprims/X_LUT3.v
vlog -work simprims_ver $xilinx_src/simprims/X_LUT4.v
vlog -work simprims_ver $xilinx_src/simprims/X_LUT5.v
vlog -work simprims_ver $xilinx_src/simprims/X_LUT6.v
vlog -work simprims_ver $xilinx_src/simprims/X_LUT7.v
vlog -work simprims_ver $xilinx_src/simprims/X_LUT8.v
vlog -work simprims_ver $xilinx_src/simprims/X_MULT18X18.v
vlog -work simprims_ver $xilinx_src/simprims/X_MULT18X18S.v
vlog -work simprims_ver $xilinx_src/simprims/X_MULT18X18SIO.v
vlog -work simprims_ver $xilinx_src/simprims/X_MUX2.v
vlog -work simprims_ver $xilinx_src/simprims/X_MUXDDR.v
vlog -work simprims_ver $xilinx_src/simprims/X_OBUF.v
vlog -work simprims_ver $xilinx_src/simprims/X_OBUFDS.v
vlog -work simprims_ver $xilinx_src/simprims/X_OBUFT.v
vlog -work simprims_ver $xilinx_src/simprims/X_OBUFTDS.v
vlog -work simprims_ver $xilinx_src/simprims/X_ODDR2.v
vlog -work simprims_ver $xilinx_src/simprims/X_ODDR.v
vlog -work simprims_ver $xilinx_src/simprims/X_ONE.v
vlog -work simprims_ver $xilinx_src/simprims/X_OPAD.v
vlog -work simprims_ver $xilinx_src/simprims/X_OR2.v
vlog -work simprims_ver $xilinx_src/simprims/X_OR3.v
vlog -work simprims_ver $xilinx_src/simprims/X_OR4.v
vlog -work simprims_ver $xilinx_src/simprims/X_OR5.v
vlog -work simprims_ver $xilinx_src/simprims/X_OR6.v
vlog -work simprims_ver $xilinx_src/simprims/X_OR7.v
vlog -work simprims_ver $xilinx_src/simprims/X_OR8.v
vlog -work simprims_ver $xilinx_src/simprims/X_OR9.v
vlog -work simprims_ver $xilinx_src/simprims/X_OR16.v
vlog -work simprims_ver $xilinx_src/simprims/X_OR32.v
vlog -work simprims_ver $xilinx_src/simprims/X_OSERDES.v
vlog -work simprims_ver $xilinx_src/simprims/X_PD.v
vlog -work simprims_ver $xilinx_src/simprims/X_PLL_ADV.v
vlog -work simprims_ver $xilinx_src/simprims/X_PMCD.v
vlog -work simprims_ver $xilinx_src/simprims/X_PPC405.v
vlog -work simprims_ver $xilinx_src/simprims/X_PPC405_ADV.v
vlog -work simprims_ver $xilinx_src/simprims/X_PU.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAM32M.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAM64M.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S1.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S1_S1.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S1_S2.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S1_S4.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S1_S8.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S1_S16.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S2.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S2_S2.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S2_S4.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S2_S8.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S2_S16.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S4.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S4_S4.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S4_S8.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S4_S16.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S8.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S8_S8.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S8_S16.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S16.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S16_S16.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S1.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S1_S1.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S1_S2.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S1_S4.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S1_S9.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S1_S18.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S1_S36.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S2.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S2_S2.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S2_S4.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S2_S9.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S2_S18.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S2_S36.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S4.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S4_S4.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S4_S9.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S4_S18.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S4_S36.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S9.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S9_S9.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S9_S18.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S9_S36.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S18.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S18_S18.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S18_S36.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S36.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S36_S36.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB18.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB18SDP.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB36_EXP.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB36SDP_EXP.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMD16.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMD32.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMD64.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMD64_ADV.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMD128.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMS16.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMS32.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMS64.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMS64_ADV.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMS128.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMS256.v
vlog -work simprims_ver $xilinx_src/simprims/X_SFF.v
vlog -work simprims_ver $xilinx_src/simprims/X_SRL16E.v
vlog -work simprims_ver $xilinx_src/simprims/X_SRLC16E.v
vlog -work simprims_ver $xilinx_src/simprims/X_SRLC32E.v
vlog -work simprims_ver $xilinx_src/simprims/X_SUH.v
vlog -work simprims_ver $xilinx_src/simprims/X_SYSMON.v
vlog -work simprims_ver $xilinx_src/simprims/X_TRI.v
vlog -work simprims_ver $xilinx_src/simprims/X_UPAD.v
vlog -work simprims_ver $xilinx_src/simprims/X_XOR2.v
vlog -work simprims_ver $xilinx_src/simprims/X_XOR3.v
vlog -work simprims_ver $xilinx_src/simprims/X_XOR4.v
vlog -work simprims_ver $xilinx_src/simprims/X_XOR5.v
vlog -work simprims_ver $xilinx_src/simprims/X_XOR6.v
vlog -work simprims_ver $xilinx_src/simprims/X_XOR7.v
vlog -work simprims_ver $xilinx_src/simprims/X_XOR8.v
vlog -work simprims_ver $xilinx_src/simprims/X_XOR16.v
vlog -work simprims_ver $xilinx_src/simprims/X_XOR32.v
3. Close Modelsim.
4. Edit C:\Modeltech_6.0\modelsim.ini . add :
simprims_ver = $MODEL_TECH/../simprims_ver
save the C:\Modeltech_6.0\modelsim.ini.
Now your Modelsim is ready to simulate using SIMPRIM library using the following command :
vsim -L simprims_ver work.glbl work.your_testbench
Sunny Arief SUDIRO said
Saya coba setting library ini, tapi muncul error antara lain : # ** Error: (vlog-7) Failed to open design unit file “C:/Xilinx/verilog/src/glbl.v” in read mode.
dan beberapa lagi (lebih dari satu) : ** Error: (vlog-7) Failed to open design unit file “C:/Xilinx/verilog/src/simprims/X_AFIFO36_INTERNAL.v” in read mode.
Mohon saran dan bantuannya. Terima kasih.
Akhmad Mulyanto said
(vlog-7) artinya :
common Message # 7:
A problem occurred while trying to open the specified file in the
specified mode. Verify that the path exists and that you have the
correct permissions in the directory. Also, if any environment variables
were used in the original specification of the filename, make sure that
they are set to valid values. This message might be followed by another
message that gives more information about the problem.
Jadi kemungkinannya :
1.Salah pakai tanda petik, tanda petik ” ” dalam blog jika dicopy dan kemudian dipaste, hasilnya menjadi beda.
2.File-file verilog source tersebut tidak ada dalam direktori: C:/Xilinx/verilog/src .
Coba cari direktori simprims dari Xilinx. Apakah ISE anda yang terinstall mempunyai file-file verilog source tsb? (glb.v, X_AFIFO36_INTERNAL.v dsb).
Coba download http://www.geocities.com/akhmadm/hdl_design/Xilinx.zip
1. Ektrak Xilinx.zip di C:
2. Copy simprim.do dalam C:\Modeltech_6.0
3. Buka Modelsim, ubah direktrori ke C:\Modeltech_6.0
4. Jalankan script simprim.do
5. Tutup Modelsim
6. Tambahkan pada C:\Modeltech_6.0\modelsim.ini :
simprims_ver = $MODEL_TECH/../simprims_ver
Misalnya menjadi :
[Library]
std = $MODEL_TECH/../std
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../verilog
vital2000 = $MODEL_TECH/../vital2000
std_developerskit = $MODEL_TECH/../std_developerskit
synopsys = $MODEL_TECH/../synopsys
modelsim_lib = $MODEL_TECH/../modelsim_lib
simprims_ver = $MODEL_TECH/../simprims_ver
Simpan modelsim.ini, tutup Modelsim.
salam,
Mulyanto
Sunny Arief SUDIRO said
Terima kasih, dan saya sudah berhasil membuat simprims library ini di modelsim menggunakan fasilitas Compile HDL Library dari ISE. Namun yang menjadi permasalahan ternyata hasil Post Translate, Post Model dan Post-Route Simulation berbeda dengan Behavioral Simulation. Padahal signal hasil Behavioral Simulation sudah sesuai dg yang saya inginkan, namun hasil Post-Route dan hasil dari Logic Analyzer (setelah saya donwload ke fpga board) jauh berbeda. Mohon sarannya, sebenarnya saya ada email ke alamat mul@paume.itb.ac.id berikut attachment hasil simulation result namun gagal (failure notice). Modul yang saya buat adalah Finite State Machine untuk menghasilkan signal controller bagi sensor MBF200 supaya bisa membaca data hasil sensing. Mohon bantuannya dan jika dimungkinkan saya dapat mengirim vhdl code saya dan hasil simulasi ke alamat email bapak, sementara alamat email saya spt tercantum dalam isian diatas.
Terima kasih.
Akhmad Mulyanto said
1. Coba periksa timing-nya dulu. Apakah cukup set-up dan hold time dari register?
2. Coba desain state mechine sesuai dengan template/example dari ISE.
3. Hati-hati pada rangkaian kombinasional:
contoh verilog:
reg pindah_state;
alwalys @(enable, start) begin
if (enable && start) begin
pindah_state <= 1′b1;
end else begin
pindah_state <= 1′b0;
end
end
contoh vhdl:
Process(enable, start) begin
if (enable && start) begin
pindah_state <= 1′b1;
end else begin
pindah_state <= 1′b0;
end
endprocess;
Hindari kedua contoh diatas, gunakan cara berikut:
contoh verilog:
wire pindah_state = (enable && start) ? 1′b1:1′b0;
atau:
wire pindah_state = enable & start.
Contoh VHDL:
pindah_state = ‘1′ when (enable==’1′ and start==’1′) else ‘0′;
atau:
pindah_state <= enable AND start.
mulyanto at gmail.com
Sunny Arief SUDIRO said
Terima kasih atas sarannya, namun karena saya baru mulai belajar VHDL programming ini mohon informasi lebih detail bagaimana memeriksa timming tersebut, mohon diberi contoh.
Terima kasih,
Akhmad Mulyanto said
Pada synthesis coba buat timing requirerment, misalnya desain harus run 100 Mhz. Contoh dalam file *.ucf :
NET “CLOCK” TNM_NET = “CLOCK”;
TIMESPEC “TS_CLOCK” = PERIOD “CLOCK” 10.00 ns HIGH 50 %;
Nanti proses sintesis dan fitting akan mencoba untuk mencapai 100 Mhz. Timing yang dicapai akan direport detail, misalnya dalam file nama_project.twr, contoh :
================================================================================
Timing constraint: TS_CLOCK = PERIOD TIMEGRP “CLOCK” 10 ns HIGH 50%;
0 items analyzed, 0 timing errors detected.
——————————————————————————–
================================================================================
Timing constraint: TS_SYSTEM_DCM_CLKDV_BUF = PERIOD TIMEGRP “SYSTEM_DCM_CLKDV_BUF” TS_CLOCK * 4
HIGH 50%;
224 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 4.059ns.
——————————————————————————–
================================================================================
Timing constraint: TS_SYSTEM_DCM_CLKFX_BUF = PERIOD TIMEGRP “SYSTEM_DCM_CLKFX_BUF” TS_CLOCK / 0.4
HIGH 50%;
1223 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 20.290ns.
——————————————————————————–
All constraints were met.
Hal lain yang menjadi petunjuk adalah waveform pada simulasi, hindari waveform yang berwarna merah karena artinya:
1. Value signal tidak didefinisikan, selalu gunakan reset untuk inisialisasi semua register. Jadi dalam simulasi, selalu diawali dengan reset yang menginisialisasi semua register.
2. Setup/hold time error.
3. Asyncronous data transfer with different domain clock (transfer data dari dua register dengan clock yang berbeda). Kalau yang no 3 ini pasti akan selalu gagal di gate level simulation.
Sunny Arief SUDIRO said
Setelah mengikuti saran anda dengan menggunakan Code Examples dari ISE Language Templates, saat ini saya sudah berhasil dengan post place and route simulation dengan hasil sinyal yg baik sesuai harapan termasuk urutan state-nya, juga tidak ada pesan kesalahan serta seluruh constraint terpenuhi. Namun ketika saya donwload ke FPGA board dan melihat sinyalnya melalui logic analyzer, state tidak dimulai dari awal state ketika sinyal reset di non aktifkan. Tetapi tidak menentu kadang mulai dari state ke 9, 5 atau yg lain, tetapi tidak pernah dari state 0. Namun seluruh sinyal berikutnya sama dengan hasil simulasi, hanya awalnya saja yg berbeda, jadi sepertinya saya kehilangan beberapa state di awalnya. Mohon bantuannya kira2 dimana permasalahannya dan bagaimana solusinya. Terima kasih.
Salam,
Sunny Arief Sudiro
sunnyarief@yahoo.com
Akhmad Mulyanto said
Pada koding state, ada ada dua state yang wajib:
state wait : state yang dipilih oleh oleh reset. Selalu memulai simulasi/fpga-test dengan reset. Setelah reset diassert, state harus tetap di state wait. Untuk memulai suatu proses maka perlu input start. Jika terdapat start maka state init bisa pindah ke state berikutnya. Selalu gunakan sinyal sinyal start yang teregister (register output bukan kombinarial output).
state default : state yang dipilih jika tidak ada input/kondisi yang sesuai algoritma. state ini digunakan untuk mendeteksi trap. Jika testing masuk ke state ini, berarti algoritma FSM ada yang salah
.
Urutan case dalam FSM juga sangat berpengaruh, hati-hati dalam menentukan urutan, hati-hati dalam menentukan kontrol dari perpindahan state. Contoh desain yang digunakan untuk memulai suatu test :
module clk_delay(clk,reset_n,start);
input clk;
output reset_n;
output reg start;
reg [19:0] Cont;
wire w_reset_n = ((Cont==20′hFFFFA) || (Cont==20′hFFFFB))? 1′b0 : 1′b1;
reg reset_n;
always@(posedge clk)
begin
if((Cont==20′hFFFFD) || (Cont==20′hFFFFE))
begin
Cont <= Cont+1;
start <= 1′b1;
end
else
if(Cont!=20′hFFFFF)
begin
Cont <= Cont+1;
start <= 1′b0;
end
end
always@(posedge clk)
begin
reset_n <= w_reset_n;
end
endmodule
Sunny Arief SUDIRO said
Saya menggunakan VHDL code, dan saya masih belum bisa mengikuti contoh design diatas (Verilog ?). Saya menggunakan code spt yg ada pada Code Examples dari ISE Language Templates, terdiri dari 3 proses, SYNC_PROC, OUTPUT_DECODE ( MOORE state machine – outputs based on state only), dan NEXT_STATE_DECODE. Atau keterbatasan logic analyzer mengcapture signal ketika di running yg sangat terbatas (sehingga awal state tidak ter-capture, karena state berikutnya cukup bagus), logic analyzer yg saya pakai Textronix TL-600.
Terima kasih.
Akhmad Mulyanto said
Coba anda tulis code state machine-nya disini, biar saya bisa analisa. Logic Analyzer seharus bisa diatur kapan mulai merekam melalui sinyal trigger. Sinyal triger ini juga digunakan untuk mentrigger start dari state machine.
Sunny Arief SUDIRO said
Betul, dan saya sudah berusaha membuat trigernya tapi belum berhasil mungkin karena keterbatasan saya. Berikut VHDL code nya :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Sensor is
Port ( Clock : in STD_LOGIC;
Reset_Sensor : in STD_LOGIC;
RD,A0,WAITS : out STD_LOGIC;
WR,CSO,FIN : out STD_LOGIC;
Datas,State1 : inout STD_LOGIC_VECTOR (3 downto 0) );
end Sensor;
architecture Behavioral of Sensor is
signal count,count1 : std_logic_vector(23 downto 0) := X”000000″;
signal dir : STD_LOGIC:=’0′;
——————– internal signal ——————–
signal sRD,sA0,sWAITS : STD_LOGIC;
signal sWR,sCSO,sFIN : STD_LOGIC;
signal sstate1 : STD_LOGIC_VECTOR (3 downto 0) ;
signal sdatas : std_logic_vector( 7 downto 0);
signal sdataout : std_logic_vector( 7 downto 0);
—————————————————————
subtype STATE_TYPE is std_ulogic_vector(3 downto 0);
constant s1 : STATE_TYPE:=”0000″;
constant s2 : STATE_TYPE:=”0001″;
constant s3 : STATE_TYPE:=”0010″;
constant s4 : STATE_TYPE:=”0011″;
constant s5 : STATE_TYPE:=”0100″;
constant s6 : STATE_TYPE:=”0101″;
constant s7 : STATE_TYPE:=”0110″;
constant s8 : STATE_TYPE:=”0111″;
constant s9 : STATE_TYPE:=”1000″;
constant s10 : STATE_TYPE:=”1001″;
constant s11 : STATE_TYPE:=”1010″;
constant s12 : STATE_TYPE:=”1011″;
signal STATE,NEXTSTATE : STATE_TYPE ;
signal counts : std_logic_vector(23 downto 0):=X”000000″;
begin
—- Module FSM for Sensor Driver ——starting —
SYNC_PROC: process (Clock, Reset_Sensor) begin
if Reset_Sensor=’1′ then
STATE <= s1 ;
RD <= ‘1′;
A0 <= ‘1′;
WAITS <= ‘0′;
WR <= ‘1′;
CSO <= ‘1′;
FIN <= ‘0′;
state1 <= “0000″;
datas <= “0000″ ;
counts <= X”000000″;
elsif Clock’event and Clock=’1′ then
STATE <= NEXTSTATE ;
— sending signal to output –
RD <= sRD;
A0 <= sA0 ;
WAITS <= sWAITS;
WR <= sWR;
CSO <= sCSO;
FIN <= sFIN;
state1 <= sstate1;
datas = X”012C04″ then — 256 x 300 =76800 or maksimum data to read
counts <= X”000000″;
else
counts scso <= ‘1′ ;
sdatas <=”00000000″;
swaits <= ‘0′;
sRD <= ‘1′;
sWR <= ‘1′;
sA0 <= ‘1′;
sFin <=’0′;
sstate1 scso <= ‘0′ ;
sRD <= ‘1′;
sWR <= ‘0′;
sA0 <= ‘0′;
sFin <=’0′;
sdatas <= “00001001″;
swaits <= ‘0′;
sstate1 scso <= ‘0′ ;
sWR <= ‘1′;
sRD <= ‘1′;
sA0 <= ‘0′;
sFin <=’0′;
sdatas <= “00001001″;
swaits <= ‘0′;
sstate1 scso <= ‘0′ ;
sA0 <= ‘1′;
sWR <= ‘0′;
sRD <= ‘1′;
sFin <=’0′;
sdatas <= “00000101″;
swaits <= ‘0′;
sstate1 scso <= ‘0′ ;
sWR <= ‘1′;
sA0 <= ‘1′;
sRD <= ‘1′;
sFin <=’0′;
sdatas <= “00000101″;
swaits <= ‘0′;
sstate1 scso <= ‘0′ ;
sWR <= ‘0′;
sA0 <= ‘0′;
sRD <= ‘1′;
sFin <=’0′;
sdatas <= “00001000″;
swaits <= ‘0′;
sstate1 scso <= ‘0′ ;
sWR <= ‘1′;
sA0 <= ‘0′;
sRD <= ‘1′;
sFin <=’0′;
sdatas <= “00001000″;
swaits <= ‘0′;
sstate1 scso <= ‘0′ ;
sWR <= ‘0′;
sA0 <= ‘1′;
sRD <= ‘1′;
sFin <=’0′;
sdatas <= “00000010″;
swaits <= ‘0′;
sstate1 scso <= ‘0′ ;
sWR <= ‘1′;
sRD <= ‘1′;
sA0 <= ‘1′;
sFin <= ‘0′;
swaits <= ‘0′;
sdatas <= “00000010″;
sstate1 sfin <=’1′;
sA0 <= ‘1′;
scso <= ‘0′ ;
sWR <= ‘1′;
sRD <= ‘0′;
sdatas <=counts(7 downto 0);
swaits <= ‘1′;
sstate1 scso <= ‘0′ ;
sRD <= ‘1′;
swaits <= ‘0′;
sWR <= ‘1′;
sfin <= ‘1′;
sA0 <= ‘1′;
sdatas <=counts(7 downto 0);
sstate1 scso <= ‘1′;
sA0 <= ‘1′;
sRD <= ‘1′;
sWR <= ‘1′;
sfin <= ‘0′;
swaits <= ‘0′;
sdatas <=”11111111″;
sstate1 null ;
end case ;
end process Output_Decode ;
Next_StateDecode : process (STATE,counts)
begin
NEXTSTATE NEXTSTATE NEXTSTATE NEXTSTATE NEXTSTATE NEXTSTATE NEXTSTATE NEXTSTATE NEXTSTATE NEXTSTATE NEXTSTATE if counts >= X”012C04″ then — maksimum data to read
Nextstate <= s12;
else
Nextstate NEXTSTATE NEXTSTATE <= s1 ;
end case ;
end process Next_StateDecode ;
—- Module FSM for Sensor Driver —— Ending —
end Behavioral;
Sunny Arief SUDIRO said
Sewaktu saya tulis di Windows editing sudah bagus susunannya, tetapi begitu di submit ternyata tidak bagus. Sebenarnya saya ada mengirim ke email yg di gmail beberapa waktu yg lalu. Terima kasih atas perhatiannya. Tapi mungkin bukan vhdl code saya yg terakhir, jika berkenan akan saya kirim ke address email yg bapak inginkan, bisa kirim addressnya ke sunny@staff.gunadarma.ac.id atau sunnyarief@yahoo.com
Sunny Arief SUDIRO said
Pak Mul,
Saya posting vhdl code saya di : http://dl.free.fr/k1fb3q1jy/MySensor2_1.vhd
Mudah-mudahan bisa diakses, terima kasih atas bantuannya.
Sunny Arief SUDIRO said
Hallo Pak Mul,
Perbaikan kode berhasil di Post Place and Route Simulation dengan perubahan2 spt pada proses gengerate RST1 dan START signal (OUT Signal), menghilangkan BEGIN-END selah THEN pada file yang bapak kirim :
process (Clock )
begin
if (Clock’event and Clock=’1′) then
if Count1 < X”0000F” then
Count1 <= Count1 + ‘1′;
else
Count1 <= Count1;
end if;
end if;
end process;
———————————————————————————
RST1 <=’1′ when (Count1 < X”0000A” or Count1 < X”0000B”) else ‘0′;
sSTART<=’1′ when (Count1 = X”0000E” or Count1 = X”0000F”) else ‘0′;
START if sSTART=’1′then
NEXTSTATE <= s1 ;
else NEXTSTATE <= s1 ;
end if;
Namun berhubung board FPGA ada di tempat lain, hari ini belum mencoba dg logic analizer.
Terimakasih.
Salam,
Sunny AS
Sunny Arief SUDIRO said
Ada ketidak jelasan pada posting sebelumnya, seharusnya terdapat informasi mengenai perubahan di NEXTSTATE DECODE tidak dapat mengguanakan perintah WHEN, perubahan yg dilakukan :
Next_StateDecode : process (STATE,counts,sstart)
begin
NEXTSTATE if sSTART=’1′then
NEXTSTATE <= s1 ;
else NEXTSTATE <= s1 ;
end if;
Akhmad Mulyanto said
OK, yah coding verilog sama vhdl saya sudah campur aduk
. Lagian sudah lama tidak koding pakai VHDL, jadi lupa syntax-nya. Yang penting algoritma-nya bisa dimengerti kan.
Sunny Arief SUDIRO said
Pada code saya sebelumnya, bisa tidsak saya gunakan sinyal RESET sebagai triger logic analyzer.
Akhmad Mulyanto said
Bisa. Itu malah lebih baik.
Komunikasi Katro « Wong nDeso yang Katro said
[...] Komunikasi Katro Ditulis pada 8 April, 2008 oleh Akhmad Mulyanto Diperusahaan ada semacam group/milis, menurut saya jika ada masalah atau ada solusi masalah sebaiknya diinformasikan ke group/milis. Alasannya daripada berhari-hari (atau malah berminggu-minggu ) mencoba menyelesaikan sendiri, lebih baik dipublikasikan sehingga anggota lain dapat memberi bantuan atau ide. Menyebarkan solusi masalah juga merupakan cara berbagi ilmu. Dan bagusnya semua member dapat mengikuti komunikasi ini. “Jeleknya” seseorang bisa jadi kelihatan bodoh atau salah di semua member . Mungkin karena hal ini, engineer jarang sekali mengkomunikasikan masalah/solusi di milis/groups. Lebih efektif lagi kalau komunikasinya diwadahi blog (work log). Selain menjadi media komunikasi, juga menjadi record atas masalah2 dan solusi2. Contohnya blog ini: http://mulyanto.wordpress.com/2007/06/29/making-simprim-library-for-modelsim/ [...]
hananim_ni said