Next_StateDecode : process (STATE,counts,sstart)

begin
NEXTSTATE if sSTART=’1′then
NEXTSTATE <= s1 ;
else NEXTSTATE <= s1 ;
end if;

Perbaikan kode berhasil di Post Place and Route Simulation dengan perubahan2 spt pada proses gengerate RST1 dan START signal (OUT Signal), menghilangkan BEGIN-END selah THEN pada file yang bapak kirim :

process (Clock )
begin
if (Clock’event and Clock=’1′) then
if Count1 < X”0000F” then
Count1 <= Count1 + ‘1′;
else
Count1 <= Count1;
end if;

end if;
end process;
———————————————————————————
RST1 <=’1′ when (Count1 < X”0000A” or Count1 < X”0000B”) else ‘0′;
sSTART<=’1′ when (Count1 = X”0000E” or Count1 = X”0000F”) else ‘0′;
START if sSTART=’1′then
NEXTSTATE <= s1 ;
else NEXTSTATE <= s1 ;
end if;

Namun berhubung board FPGA ada di tempat lain, hari ini belum mencoba dg logic analizer.
Terimakasih.
Salam,

Sunny AS

Saya posting vhdl code saya di : http://dl.free.fr/k1fb3q1jy/MySensor2_1.vhd

Mudah-mudahan bisa diakses, terima kasih atas bantuannya.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Sensor is
Port ( Clock : in STD_LOGIC;
Reset_Sensor : in STD_LOGIC;
RD,A0,WAITS : out STD_LOGIC;
WR,CSO,FIN : out STD_LOGIC;
Datas,State1 : inout STD_LOGIC_VECTOR (3 downto 0) );
end Sensor;

architecture Behavioral of Sensor is

signal count,count1 : std_logic_vector(23 downto 0) := X”000000″;

signal dir : STD_LOGIC:=’0′;
——————– internal signal ——————–
signal sRD,sA0,sWAITS : STD_LOGIC;
signal sWR,sCSO,sFIN : STD_LOGIC;
signal sstate1 : STD_LOGIC_VECTOR (3 downto 0) ;
signal sdatas : std_logic_vector( 7 downto 0);
signal sdataout : std_logic_vector( 7 downto 0);
—————————————————————
subtype STATE_TYPE is std_ulogic_vector(3 downto 0);
constant s1 : STATE_TYPE:=”0000″;
constant s2 : STATE_TYPE:=”0001″;
constant s3 : STATE_TYPE:=”0010″;
constant s4 : STATE_TYPE:=”0011″;
constant s5 : STATE_TYPE:=”0100″;
constant s6 : STATE_TYPE:=”0101″;
constant s7 : STATE_TYPE:=”0110″;
constant s8 : STATE_TYPE:=”0111″;
constant s9 : STATE_TYPE:=”1000″;
constant s10 : STATE_TYPE:=”1001″;
constant s11 : STATE_TYPE:=”1010″;
constant s12 : STATE_TYPE:=”1011″;

signal STATE,NEXTSTATE : STATE_TYPE ;
signal counts : std_logic_vector(23 downto 0):=X”000000″;

begin

—- Module FSM for Sensor Driver ——starting —

SYNC_PROC: process (Clock, Reset_Sensor) begin
if Reset_Sensor=’1′ then
STATE <= s1 ;
RD <= ‘1′;
A0 <= ‘1′;
WAITS <= ‘0′;
WR <= ‘1′;
CSO <= ‘1′;
FIN <= ‘0′;
state1 <= “0000″;
datas <= “0000″ ;
counts <= X”000000″;
elsif Clock’event and Clock=’1′ then
STATE <= NEXTSTATE ;
— sending signal to output –
RD <= sRD;
A0 <= sA0 ;
WAITS <= sWAITS;
WR <= sWR;
CSO <= sCSO;
FIN <= sFIN;
state1 <= sstate1;
datas = X”012C04″ then — 256 x 300 =76800 or maksimum data to read
counts <= X”000000″;
else
counts scso <= ‘1′ ;
sdatas <=”00000000″;
swaits <= ‘0′;
sRD <= ‘1′;
sWR <= ‘1′;
sA0 <= ‘1′;
sFin <=’0′;
sstate1 scso <= ‘0′ ;
sRD <= ‘1′;
sWR <= ‘0′;
sA0 <= ‘0′;
sFin <=’0′;
sdatas <= “00001001″;
swaits <= ‘0′;
sstate1 scso <= ‘0′ ;
sWR <= ‘1′;
sRD <= ‘1′;
sA0 <= ‘0′;
sFin <=’0′;
sdatas <= “00001001″;
swaits <= ‘0′;
sstate1 scso <= ‘0′ ;
sA0 <= ‘1′;
sWR <= ‘0′;
sRD <= ‘1′;
sFin <=’0′;
sdatas <= “00000101″;
swaits <= ‘0′;
sstate1 scso <= ‘0′ ;
sWR <= ‘1′;
sA0 <= ‘1′;
sRD <= ‘1′;
sFin <=’0′;
sdatas <= “00000101″;
swaits <= ‘0′;
sstate1 scso <= ‘0′ ;
sWR <= ‘0′;
sA0 <= ‘0′;
sRD <= ‘1′;
sFin <=’0′;
sdatas <= “00001000″;
swaits <= ‘0′;
sstate1 scso <= ‘0′ ;
sWR <= ‘1′;
sA0 <= ‘0′;
sRD <= ‘1′;
sFin <=’0′;
sdatas <= “00001000″;
swaits <= ‘0′;
sstate1 scso <= ‘0′ ;
sWR <= ‘0′;
sA0 <= ‘1′;
sRD <= ‘1′;
sFin <=’0′;
sdatas <= “00000010″;
swaits <= ‘0′;
sstate1 scso <= ‘0′ ;
sWR <= ‘1′;
sRD <= ‘1′;
sA0 <= ‘1′;
sFin <= ‘0′;
swaits <= ‘0′;
sdatas <= “00000010″;

sstate1 sfin <=’1′;
sA0 <= ‘1′;
scso <= ‘0′ ;
sWR <= ‘1′;
sRD <= ‘0′;
sdatas <=counts(7 downto 0);
swaits <= ‘1′;
sstate1 scso <= ‘0′ ;
sRD <= ‘1′;
swaits <= ‘0′;
sWR <= ‘1′;
sfin <= ‘1′;
sA0 <= ‘1′;
sdatas <=counts(7 downto 0);
sstate1 scso <= ‘1′;
sA0 <= ‘1′;
sRD <= ‘1′;
sWR <= ‘1′;
sfin <= ‘0′;
swaits <= ‘0′;
sdatas <=”11111111″;
sstate1 null ;
end case ;

end process Output_Decode ;

Next_StateDecode : process (STATE,counts)

begin
NEXTSTATE NEXTSTATE NEXTSTATE NEXTSTATE NEXTSTATE NEXTSTATE NEXTSTATE NEXTSTATE NEXTSTATE NEXTSTATE NEXTSTATE if counts >= X”012C04″ then — maksimum data to read
Nextstate <= s12;
else
Nextstate NEXTSTATE NEXTSTATE <= s1 ;
end case ;

end process Next_StateDecode ;
—- Module FSM for Sensor Driver —— Ending —

end Behavioral;