Verilog task for loading text file to registers

CODE :

integer data [255:0];

task read_file;
input integer i_infile;
input integer numdata;
input integer indeks_init;
input reg [7:0] file_type;
input display_testvector;

integer indeks;
integer kolom,baris;
integer i_c,i_r,i;

reg file_opened,file_closed;

begin
//$display("============= %s ======================",file_type);
file_opened = 1'b0;
file_closed = 1'b0;
i_c = 0;
i_r = 0;
indeks = indeks_init;

for(i=0; i<(numdata); i=i+1)
begin
data[i] = 0;
end

if (i_infile ==0) // If error opening file
begin
$display("File input not found !!!!!!!");
disable file_input_block; // Just quit
end
else
begin
file_opened = 1'b1;
end

if (~file_closed & file_opened)
begin
i_c = $fgetc(i_infile);
//$display("%8x", i_c);
while (i_c != `EOF)//
begin
if (i_c == "/")
begin
i_r = $ungetc(i_c, i_infile);
//$display("COMMENT");
i_c = $fgets(line, i_infile); // Read the comment
if (display_testvector == 1'b1)
begin
$display("%s", line);
end
end
else
begin

i_r = $ungetc(i_c, i_infile); // PuSH char back
if(file_type=="h") begin
i_c = $fscanf(i_infile,"%x",data[indeks]);
end else begin
i_c = $fscanf(i_infile,"%d",data[indeks]);
end

if (display_testvector == 1'b1)
begin
$display(" data[%8d] = %8x",indeks,data[indeks]);
end
indeks = indeks + 1;
end

i_c = $fgetc(i_infile);
//$display("%8x", i_c);
if(indeks==numdata)
begin
i_c = `EOF;
end

end
$fclose(i_infile);
file_closed = 1'b1;
end
end
endtask

HOW TO USE THE TASK :

1. Add task read_file in your verilog tesbench.
2. Call the task, example:


integer i_infile;

initial
begin : file_input_block
starter = 1'b0;
//----------------------------------------
//read file test vector test_in.txt
//----------------------------------------
i_infile1 = $fopen("./testvector/test_in.txt", "r");
read_file(i_infile1,256,1,"d",0);
for(i=0; i<(256); i=i+1) begin
regfile[i] = data[i];
end

//starting the test
starter = 1'b1;

dut dut_inst (
.clk (clk)
,.addr (addr)
,.datain (regfile[addr])
);

end