The Devil In The Detail

Important Notes that forgotten [mulyanto at gmail dot com]

Archive for the ‘Embedded System’ Category

Information on LEON3 Simulation

Posted by mulyanto on March 28, 2008

http://tech.groups.yahoo.com/group/leon_sparc/message/12106

Re: [leon_sparc] Running test program on leon in modelsim

You do not want to simulate a mkprom image in VHDL, trust me.
Even the smallest image will execute ~ 1,000,000 instructions
before entering main() in RAM. This is only ~ 30 ms on real
hardware at 50 MHz, but ~ 10 hours in VHDL (on a fast host).

You can easily see in TSIM how many instructions you will need:

sparc-elf-gcc -msoft-float hello.c -o hello.exe -lsmall
sparc-elf-mkprom hello.exe -nocomp -nomsg

tsim-leon3 prom.out
.
.
section: .text, addr: 0×0, size 34304 bytes
read 103 symbols
tsim> bre 0×40000000
breakpoint 1 at 0×40000000: .bdata
tsim> run
breakpoint 1 .bdata
tsim> per

Cycles : 1399497
Instructions : 906783
Overall CPI : 1.54

CPU performance (50.0 MHz) : 32.40 MOPS (32.40 MIPS, 0.00 MFLOPS)
Cache hit rate : 98.7 % (100.0 / 80.0)
AHB bandwidth utilisation : 33.7 % ( 0.4 / 33.3)
Simulated time : 27.99 ms
Processor utilisation : 100.00 %
Real-time performance : 11.86 %
Simulator performance : 3843.69 KIPS
Used time (sys + user) : 0.24 s

So even if we created the smallest possible binary using -lsmall
and fastest mkprom loading with -nomsg and -nocomp, you will need
to execute 906,783 instructions to get to RAM, and then maybe an
other 10,000 to get to main(). This is why the test bench in leon3
designs does NOT use mkprom, but a simple assembly reset sequence
and a pre-loaded RAM image…

Jiri.

sacliv wrote:
> Hey guys, I’m trying to load a test c program i wrote on the leon3 in
> the vhdl leon3 code and run it in modelsim to view the waveforms.
>
> I followed the bcc manual and did mkprom on my executable, and then i
> copied the .srec file to the testbench directory, and in the
> testbench.vhd, i changed the filename of the prom.srec to test.srec,
> which is my srec file.
>
> The test program is very simple and just prints out hello world, but
> in the modelsim simulation of the leon3, i’m watching the pc and
> instructions of the leon3 core, but i can’t seem to get to my test
> program.
>
> Does anyone know either how long i have to simulate it until before i
> get to main() in my test program? Or if i’m doing it wrong, what’s the
> correct procedure? Thanks!

================================================================================================
http://tech.groups.yahoo.com/group/leon_sparc/message/12108

Re: [leon_sparc] Re: Running test program on leon in modelsim

See how the test bench is compiled by doing ‘make soft’ in the
template design directory. The final command will be:

sparc-elf-gcc -I../../software/leon3 -O2 -g -msoft-float systest.c -L./
lib3tests.a -o systest.exe
sparc-elf-objcopy -O srec systest.exe sram.srec

You can do pretty much the same using your own application:

sparc-elf-gcc -O2 -g -msoft-float myapp.c -o myapp.exe
sparc-elf-objcopy -O srec myapp.exe sram.srec

And make sure you understand how to use the ‘volatile’ keyword
in C if you intend to do any memory tests or similar …

Jiri.

sacliv wrote:
> Wow that’s good to know. So is there a way to easily simulate my test
> code using the leon3 VHDL code?

================================================================================================

http://tech.groups.yahoo.com/group/leon_sparc/message/12114

Re: [leon_sparc] Re: Running test program on leon in modelsim

You can run your code from PROM for fastest run-time. Copy prom.S
from software/leon3 to you local template design, and do ‘make soft’.
Then, add your instructions just before the code jumps to RAM at
the end of the file:

set RAMSTART, %g1
<–insert here
jmp %g1
nop

Do a ‘make soft’ again, and restart simulation. Note that you can
get assembly output from the simulation by setting the disas generic
to 1 (or start modelsim with -gdisas=1) .

Jiri.

================================================================================================

http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=92&Itemid=66

How do I put the content of a file “as is” into the .data section (or somewhere else into memory)?
You can add a binary file to an existing elf file with objcopy, by adding a new section and fill it with the desired content:

sparc-elf-objcopy –add-section .myelfsection=file.bin –change-section-address .myelfsection=0×00001000

–set-section-flags .myelfsection=alloc,contents,load,data file.exe

The example above adds the file ‘file.bin’ to the elf file ‘file.exe’ at address 0×1000. Note that this is done after linking.

================================================================================================

Posted in Embedded System, Modelsim | 4 Comments »

Using GRMON with USB-Serial Device

Posted by mulyanto on February 13, 2008

The Command :

grmon-eval -nosram /dev/ttyUSB0

or

grmon-eval -nosram /dev/ttyUSB1

Posted in Embedded System | Leave a Comment »

Using GRMON with Altera ByteBlaster

Posted by mulyanto on January 10, 2008

The command is :

grmon-eval.exe -u -altjtag

altjtag.jpg

Implementation of LEON3 on Nios Stratix EP1S40F780C5 use the following command:

grmon-eval.exe -altjtag -nosram

The linux image downloaded to sdram at 0×40000000 and the console connected to AHB uart (J19). The debug uart (j27) not used. If -nosram not used then sdram address will be indentified at 0×60000000.

Posted in Altera, Embedded System | Leave a Comment »

C Code for AHB RAM LEON access

Posted by mulyanto on September 8, 2007

Here is the c code to write-read on AHB RAM. The AHB RAM is slave adressed in 0×40000000 – 0×40100000;

ahbram.pdf

Use :

sparc-elf-gcc -msoft-float -g -O2 ahbram.c -o ahbram.exe

Posted in C++ Code, Embedded System | 2 Comments »

Running program from AHBRAM in LEON

Posted by mulyanto on September 3, 2007

1. First make sure that the size of AHBRAM is enough for the program. The following h.c :

main()
{
printf(“H”);
}

need at least 16 Kb AHBRAM.

2. run command “info sys” in grlib :

grlib> info sys

You will get the information like this:

sys-info-leon3.jpg

It means that the AHB RAM have address a00000000 – a0100000

3. Compile the H.c :

sparc-elf-gcc -Ttext=0xa0000000 -msoft-float -g -O2 h.c -o h.exe

4. Load to leon

grlib> lo h.exe

5. Run the h.exe

grlib> run

Posted in Altera, C++ Code, Embedded System | Leave a Comment »

Nios Stratix EP1S40F780C5 qsf for LEON3

Posted by mulyanto on August 28, 2007

Posted in Altera, Embedded System | Leave a Comment »

Compiler Setting File (csf) of LEON2 on Nios Development (Stratix) board

Posted by mulyanto on April 24, 2007

COMPILER_SETTINGS
{
IO_PLACEMENT_OPTIMIZATION = ON;
ENABLE_DRC_SETTINGS = OFF;
PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF;
PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF;
PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF;
DRC_FANOUT_EXCEEDING = 30;
DRC_REPORT_FANOUT_EXCEEDING = OFF;
DRC_TOP_FANOUT = 50;
DRC_REPORT_TOP_FANOUT = OFF;
RUN_DRC_DURING_COMPILATION = OFF;
ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON;
ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF;
ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF;
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF;
SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF;
MERGE_HEX_FILE = OFF;
TRUE_WYSIWYG_FLOW = OFF;
SEED = 1;
FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY;
FAMILY = STRATIX;
DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = “DPRAM0 TO 1 DPRAM1 TO 2″;
DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = “MEGALAB COLUMN 1″;
DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = “MEGALAB COLUMN 1″;
DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = “DPRAM0 TO 1 DPRAM1 TO 2″;
DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = “LOWER TO 1ESB UPPER TO 1″;
DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = “MEGALAB COLUMN 1″;
DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = “DPRAM0 TO 1 DPRAM1 TO 2″;
DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = “MEGALAB COLUMN 1″;
DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = “MEGALAB COLUMN 1″;
DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = “DPRAM0 TO 3 DPRAM1 TO 4″;
DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = “DPRAM0 TO 3 DPRAM1 TO 4″;
DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = “MEGALAB COLUMN 3″;
DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = “MEGALAB COLUMN 3″;
DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = “DPRAM0 TO 3 DPRAM1 TO 4ESB”;
DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = “DPRAM0 TO 3 DPRAM1 TO 4ESB”;
DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = “LOWER TO 3 UPPER TO 4ESB”;
DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = “MEGALAB COLUMN 3″;
DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = “DPRAM0 TO 3 DPRAM1 TO 4″;
DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = “DPRAM0 TO 3 DPRAM1 TO 4″;
DPRAM_WIDE_MODE_INPUT_EPXA4_10 = “LOWER TO 3 UPPER TO 4″;
DPRAM_DEEP_MODE_INPUT_EPXA4_10 = “MEGALAB COLUMN 3″;
DPRAM_OTHER_SIGNALS_EPXA4_10 = “DEFAULT OTHER ROUTING OPTIONS”;
DPRAM_OUTPUT_EPXA4_10 = “DEFAULT OUTPUT ROUTING OPTIONS”;
DPRAM_INPUT_EPXA4_10 = “DEFAULT INPUT ROUTING OPTIONS”;
STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = “MEGALAB COLUMN 2″;
PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = “MEGALAB COLUMN 2″;
PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = “MEGALAB COLUMN 2″;
STRIPE_TO_PLD_BRIDGE_EPXA4_10 = “MEGALAB COLUMN 1″;
FAST_FIT_COMPILATION = OFF;
SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF;
OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON;
OPTIMIZE_TIMING = NORMAL_COMPILATION;
OPTIMIZE_HOLD_TIMING = “IO PATHS AND MINIMUM TPD PATHS”;
COMPILATION_LEVEL = FULL;
SAVE_DISK_SPACE = ON;
SPEED_DISK_USAGE_TRADEOFF = NORMAL;
LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF;
SIGNALPROBE_ALLOW_OVERUSE = OFF;
FOCUS_ENTITY_NAME = |leon_stratix;
}
DEFAULT_DEVICE_OPTIONS
{
GENERATE_CONFIG_HEXOUT_FILE = OFF;
GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
GENERATE_CONFIG_JBC_FILE = OFF;
GENERATE_CONFIG_JAM_FILE = OFF;
GENERATE_CONFIG_ISC_FILE = OFF;
GENERATE_CONFIG_SVF_FILE = OFF;
GENERATE_JBC_FILE_COMPRESSED = ON;
GENERATE_JBC_FILE = OFF;
GENERATE_JAM_FILE = OFF;
GENERATE_ISC_FILE = OFF;
GENERATE_SVF_FILE = OFF;
RESERVE_PIN = “AS INPUT TRI-STATED”;
RESERVE_ALL_UNUSED_PINS = “AS OUTPUT DRIVING GROUND”;
HEXOUT_FILE_COUNT_DIRECTION = UP;
HEXOUT_FILE_START_ADDRESS = 0;
GENERATE_HEX_FILE = OFF;
GENERATE_RBF_FILE = OFF;
GENERATE_TTF_FILE = OFF;
RESERVE_ASDO_AFTER_CONFIGURATION = “USE AS REGULAR IO”;
RESERVE_DATA0_AFTER_CONFIGURATION = “AS INPUT TRI-STATED”;
RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = “USE AS REGULAR IO”;
RESERVE_RDYNBUSY_AFTER_CONFIGURATION = “USE AS REGULAR IO”;
RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = “USE AS REGULAR IO”;
DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
STRATIX_CONFIGURATION_DEVICE = AUTO;
CYCLONE_CONFIGURATION_DEVICE = AUTO;
FLEX10K_CONFIGURATION_DEVICE = AUTO;
FLEX6K_CONFIGURATION_DEVICE = AUTO;
MERCURY_CONFIGURATION_DEVICE = AUTO;
EXCALIBUR_CONFIGURATION_DEVICE = AUTO;
APEX20K_CONFIGURATION_DEVICE = AUTO;
USE_CONFIGURATION_DEVICE = ON;
ENABLE_INIT_DONE_OUTPUT = OFF;
FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
ENABLE_DEVICE_WIDE_OE = OFF;
ENABLE_DEVICE_WIDE_RESET = OFF;
RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
AUTO_RESTART_CONFIGURATION = OFF;
ENABLE_VREFB_PIN = OFF;
ENABLE_VREFA_PIN = OFF;
SECURITY_BIT = OFF;
USER_START_UP_CLOCK = OFF;
APEXII_CONFIGURATION_SCHEME = “PASSIVE SERIAL”;
FLEX10K_CONFIGURATION_SCHEME = “PASSIVE SERIAL”;
FLEX6K_CONFIGURATION_SCHEME = “PASSIVE SERIAL”;
MERCURY_CONFIGURATION_SCHEME = “PASSIVE SERIAL”;
EXCALIBUR_CONFIGURATION_SCHEME = “PASSIVE SERIAL”;
CYCLONE_CONFIGURATION_SCHEME = “ACTIVE SERIAL”;
STRATIX_CONFIGURATION_SCHEME = “PASSIVE SERIAL”;
APEX20K_CONFIGURATION_SCHEME = “PASSIVE SERIAL”;
STRATIX_UPDATE_MODE = STANDARD;
USE_CHECKSUM_AS_USERCODE = OFF;
MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
MAX7000_JTAG_USER_CODE = FFFFFFFF;
FLEX10K_JTAG_USER_CODE = 7F;
MERCURY_JTAG_USER_CODE = FFFFFFFF;
APEX20K_JTAG_USER_CODE = FFFFFFFF;
STRATIX_JTAG_USER_CODE = FFFFFFFF;
MAX7000S_JTAG_USER_CODE = FFFF;
RESERVE_NCEO_AFTER_CONFIGURATION = “USE AS REGULAR IO”;
FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
ENABLE_JTAG_BST_SUPPORT = OFF;
CONFIGURATION_CLOCK_DIVISOR = 1;
CONFIGURATION_CLOCK_FREQUENCY = “10 MHZ”;
CLOCK_SOURCE = INTERNAL;
COMPRESSION_MODE = OFF;
ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
}
AUTO_SLD_HUB_ENTITY
{
AUTO_INSERT_SLD_HUB_ENTITY = ENABLE;
HUB_INSTANCE_NAME = SLD_HUB_INST;
HUB_ENTITY_NAME = SLD_HUB;
}
CHIP(leon)
{
DEVICE = EP1S40F780C5;
PLD_CLOCKINPUT : LOCATION = Pin_K17;
SDRAM_CLK : LOCATION = Pin_E15;
FSE_A[0] : LOCATION = Pin_A4;
FSE_A[1] : LOCATION = Pin_A3;
FSE_A[2] : LOCATION = Pin_B3;
FSE_A[3] : LOCATION = Pin_B5;
FSE_A[4] : LOCATION = Pin_B4;
FSE_A[5] : LOCATION = Pin_C4;
FSE_A[6] : LOCATION = Pin_A5;
FSE_A[7] : LOCATION = Pin_C5;
FSE_A[8] : LOCATION = Pin_D5;
FSE_A[9] : LOCATION = Pin_E6;
FSE_A[10] : LOCATION = Pin_A6;
FSE_A[11] : LOCATION = Pin_B7;
FSE_A[12] : LOCATION = Pin_D6;
FSE_A[13] : LOCATION = Pin_A7;
FSE_A[14] : LOCATION = Pin_D7;
FSE_A[15] : LOCATION = Pin_C6;
FSE_A[16] : LOCATION = Pin_C7;
FSE_A[17] : LOCATION = Pin_B6;
FSE_A[18] : LOCATION = Pin_D8;
FSE_A[19] : LOCATION = Pin_C8;
FSE_A[20] : LOCATION = Pin_E8;
FSE_A[21] : LOCATION = Pin_D9;
FSE_A[22] : LOCATION = Pin_B9;
FSE_D[0] : LOCATION = Pin_H12;
FSE_D[1] : LOCATION = Pin_F12;
FSE_D[2] : LOCATION = Pin_J12;
FSE_D[3] : LOCATION = Pin_M12;
FSE_D[4] : LOCATION = Pin_H17;
FSE_D[5] : LOCATION = Pin_K18;
FSE_D[6] : LOCATION = Pin_H18;
FSE_D[7] : LOCATION = Pin_G18;
FSE_D[8] : LOCATION = Pin_B8;
FSE_D[9] : LOCATION = Pin_A8;
FSE_D[10] : LOCATION = Pin_A9;
FSE_D[11] : LOCATION = Pin_C9;
FSE_D[12] : LOCATION = Pin_E10;
FSE_D[13] : LOCATION = Pin_A10;
FSE_D[14] : LOCATION = Pin_C10;
FSE_D[15] : LOCATION = Pin_B10;
FSE_D[16] : LOCATION = Pin_A11;
FSE_D[17] : LOCATION = Pin_C11;
FSE_D[18] : LOCATION = Pin_D11;
FSE_D[19] : LOCATION = Pin_B11;
FSE_D[20] : LOCATION = Pin_D10;
FSE_D[21] : LOCATION = Pin_G10;
FSE_D[22] : LOCATION = Pin_F10;
FSE_D[23] : LOCATION = Pin_H11;
FSE_D[24] : LOCATION = Pin_G11;
FSE_D[25] : LOCATION = Pin_F8;
FSE_D[26] : LOCATION = Pin_J9;
FSE_D[27] : LOCATION = Pin_J13;
FSE_D[28] : LOCATION = Pin_L13;
FSE_D[29] : LOCATION = Pin_M11;
FSE_D[30] : LOCATION = Pin_L11;
FSE_D[31] : LOCATION = Pin_G7;
SRAM_BE_N[0] : LOCATION = Pin_M18;
SRAM_BE_N[1] : LOCATION = Pin_F17;
SRAM_BE_N[2] : LOCATION = Pin_J18;
SRAM_BE_N[3] : LOCATION = Pin_L17;
FLASH_OE_N : LOCATION = Pin_F19;
FLASH_RW_N : LOCATION = Pin_G19;
SRAM_OE_N : LOCATION = Pin_B26;
FLASH_CS_N : LOCATION = Pin_K19;
SRAM_CS_N : LOCATION = Pin_B24;
SRAM_WE_N : LOCATION = Pin_C24;
SDRAM_DQ[0] : LOCATION = Pin_AH4;
SDRAM_DQ[1] : LOCATION = Pin_AE5;
SDRAM_DQ[2] : LOCATION = Pin_AG3;
SDRAM_DQ[3] : LOCATION = Pin_AG5;
SDRAM_DQ[4] : LOCATION = Pin_AG4;
SDRAM_DQ[5] : LOCATION = Pin_AF4;
SDRAM_DQ[6] : LOCATION = Pin_AH5;
SDRAM_DQ[7] : LOCATION = Pin_AF5;
SDRAM_DQ[8] : LOCATION = Pin_AE6;
SDRAM_DQ[9] : LOCATION = Pin_AG6;
SDRAM_DQ[10] : LOCATION = Pin_AH6;
SDRAM_DQ[11] : LOCATION = Pin_AD6;
SDRAM_DQ[12] : LOCATION = Pin_AF7;
SDRAM_DQ[13] : LOCATION = Pin_AH7;
SDRAM_DQ[14] : LOCATION = Pin_AG7;
SDRAM_DQ[15] : LOCATION = Pin_AF6;
SDRAM_DQ[16] : LOCATION = Pin_AG8;
SDRAM_DQ[17] : LOCATION = Pin_AF8;
SDRAM_DQ[18] : LOCATION = Pin_AD8;
SDRAM_DQ[19] : LOCATION = Pin_AH9;
SDRAM_DQ[20] : LOCATION = Pin_AH8;
SDRAM_DQ[21] : LOCATION = Pin_AE9;
SDRAM_DQ[22] : LOCATION = Pin_AF9;
SDRAM_DQ[23] : LOCATION = Pin_AG9;
SDRAM_DQ[24] : LOCATION = Pin_AD10;
SDRAM_DQ[25] : LOCATION = Pin_AF10;
SDRAM_DQ[26] : LOCATION = Pin_AH10;
SDRAM_DQ[27] : LOCATION = Pin_AE10;
SDRAM_DQ[28] : LOCATION = Pin_AF11;
SDRAM_DQ[29] : LOCATION = Pin_AE11;
SDRAM_DQ[30] : LOCATION = Pin_AH11;
SDRAM_DQ[31] : LOCATION = Pin_AG11;
SDRAM_A[0] : LOCATION = Pin_AE4;
SDRAM_A[1] : LOCATION = Pin_W12;
SDRAM_A[2] : LOCATION = Pin_AC11;
SDRAM_A[3] : LOCATION = Pin_W10;
SDRAM_A[4] : LOCATION = Pin_AA11;
SDRAM_A[5] : LOCATION = Pin_AC10;
SDRAM_A[6] : LOCATION = Pin_AB11;
SDRAM_A[7] : LOCATION = Pin_AC8;
SDRAM_A[8] : LOCATION = Pin_AB10;
SDRAM_A[9] : LOCATION = Pin_V11;
SDRAM_A[10] : LOCATION = Pin_Y11;
SDRAM_A[11] : LOCATION = Pin_AB7;
SDRAM_DQM[0] : LOCATION = Pin_AE14;
SDRAM_DQM[1] : LOCATION = Pin_Y13;
SDRAM_DQM[2] : LOCATION = Pin_AE7;
SDRAM_DQM[3] : LOCATION = Pin_AG10;
SDRAM_BA[0] : LOCATION = Pin_AG19;
SDRAM_BA[1] : LOCATION = Pin_AF19;
SDRAM_CKE : LOCATION = Pin_AE18;
SDRAM_CS_N : LOCATION = Pin_AG18;
SDRAM_WE_N : LOCATION = Pin_AH19;
SDRAM_RAS_N : LOCATION = Pin_AH3;
SDRAM_CAS_N : LOCATION = Pin_AD18;
cf_ide_a[0] : LOCATION = Pin_L9;
cf_ide_a[1] : LOCATION = Pin_J3;
cf_ide_a[2] : LOCATION = Pin_L10;
cf_ide_a[3] : LOCATION = Pin_L6;
cf_ide_a[4] : LOCATION = Pin_H1;
cf_ide_a[5] : LOCATION = Pin_H2;
cf_ide_a[6] : LOCATION = Pin_L8;
cf_ide_a[7] : LOCATION = Pin_L7;
cf_ide_a[8] : LOCATION = Pin_H3;
cf_ide_a[9] : LOCATION = Pin_K3;
cf_ide_a[10] : LOCATION = Pin_M7;
cf_ide_data[0] : LOCATION = Pin_N3;
cf_ide_data[1] : LOCATION = Pin_L2;
cf_ide_data[2] : LOCATION = Pin_N8;
cf_ide_data[3] : LOCATION = Pin_M4;
cf_ide_data[4] : LOCATION = Pin_N6;
cf_ide_data[5] : LOCATION = Pin_N1;
cf_ide_data[6] : LOCATION = Pin_N9;
cf_ide_data[7] : LOCATION = Pin_P3;
cf_ide_data[8] : LOCATION = Pin_N10;
cf_ide_data[9] : LOCATION = Pin_M2;
cf_ide_data[10] : LOCATION = Pin_N5;
cf_ide_data[11] : LOCATION = Pin_M3;
cf_ide_data[12] : LOCATION = Pin_N7;
cf_ide_data[13] : LOCATION = Pin_L1;
cf_ide_data[14] : LOCATION = Pin_N4;
cf_ide_data[15] : LOCATION = Pin_L3;
cf_ide_pdiag : LOCATION = Pin_M8;
cf_ide_dasp : LOCATION = Pin_AD23;
CF_PRESENT_N : LOCATION = Pin_R3;
cf_ide_cs0n : LOCATION = Pin_J2;
cf_ide_cs1n : LOCATION = Pin_K8;
cf_ide_csel : LOCATION = Pin_K2;
cf_ide_inpack : LOCATION = Pin_J4;
cf_ide_IORDn : LOCATION = Pin_M9;
cf_ide_IOWRn : LOCATION = Pin_M10;
CF_ATASEL_N : LOCATION = Pin_K7;
cf_ide_INTRQ : LOCATION = Pin_M5;
cf_ide_reg : LOCATION = Pin_V18;
cf_ide_IORDY : LOCATION = Pin_K1;
cf_ide_we : LOCATION = Pin_L5;
cf_ide_IOSn : LOCATION = Pin_AG24;
CF_POWER : LOCATION = Pin_H4;
ENET_BE_N[0] : LOCATION = Pin_T22;
ENET_BE_N[1] : LOCATION = Pin_U26;
ENET_BE_N[2] : LOCATION = Pin_U25;
ENET_BE_N[3] : LOCATION = Pin_T19;
ENET_AEN : LOCATION = Pin_V28;
ENET_ADS_N : LOCATION = Pin_V25;
ENET_LCLK : LOCATION = Pin_R26;
ENET_IOCHRDY : LOCATION = Pin_V26;
ENET_RDYRTN_N : LOCATION = Pin_T28;
ENET_SRDY_N : LOCATION = Pin_T25;
ENET_INTRQ : LOCATION = Pin_V27;
ENET_LDEV_N : LOCATION = Pin_T26;
ENET_IOR_N : LOCATION = Pin_T23;
ENET_IOW_N : LOCATION = Pin_T24;
ENET_DATACS_N : LOCATION = Pin_T20;
ENET_CYCLE_N : LOCATION = Pin_U27;
ENET_W_R_N : LOCATION = Pin_T21;
USER_PB[0] : LOCATION = Pin_W5;
USER_PB[1] : LOCATION = Pin_W6;
USER_PB1[0] : LOCATION = Pin_AB2;
USER_PB1[1] : LOCATION = Pin_AB1;
LEDG[0] : LOCATION = Pin_H27;
LEDG[1] : LOCATION = Pin_H28;
LEDG[2] : LOCATION = Pin_L23;
LEDG[3] : LOCATION = Pin_L24;
LEDG[4] : LOCATION = Pin_J25;
LEDG[5] : LOCATION = Pin_J26;
LEDG[6] : LOCATION = Pin_L20;
LEDG[7] : LOCATION = Pin_L19;
RXD1 : LOCATION = Pin_Y28;
RXD2 : LOCATION = Pin_AA28;
TXD1 : LOCATION = Pin_U21;
TXD2 : LOCATION = Pin_V24;
PROGMEM[0] : LOCATION = Pin_C21;
PROGMEM[1] : LOCATION = Pin_B21;
PROGMEM[2] : LOCATION = Pin_A21;
PROGMEM[3] : LOCATION = Pin_C20;
PROGMEM[4] : LOCATION = Pin_A20;
PROGMEM[5] : LOCATION = Pin_B20;
PROGMEM[6] : LOCATION = Pin_B18;
PROGMEM[7] : LOCATION = Pin_D21;
PROGMEM[8] : LOCATION = Pin_E19;
PROGMEM[9] : LOCATION = Pin_C19;
PROGMEM[10] : LOCATION = Pin_B19;
PROGMEM[11] : LOCATION = Pin_A19;
PROGMEM[12] : LOCATION = Pin_D18;
PROGMEM[13] : LOCATION = Pin_C18;
PROGMEM[14] : LOCATION = Pin_A18;
PROGMEM[15] : LOCATION = Pin_D19;
AUTO_RESTART_CONFIGURATION = OFF;
RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
USER_START_UP_CLOCK = OFF;
ENABLE_DEVICE_WIDE_RESET = OFF;
ENABLE_DEVICE_WIDE_OE = OFF;
ENABLE_INIT_DONE_OUTPUT = OFF;
FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
ENABLE_JTAG_BST_SUPPORT = OFF;
MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
APEX20K_JTAG_USER_CODE = FFFFFFFF;
MERCURY_JTAG_USER_CODE = FFFFFFFF;
FLEX10K_JTAG_USER_CODE = 7F;
MAX7000_JTAG_USER_CODE = FFFFFFFF;
MAX7000S_JTAG_USER_CODE = FFFF;
STRATIX_JTAG_USER_CODE = FFFFFFFF;
APEX20K_CONFIGURATION_SCHEME = “PASSIVE SERIAL”;
MERCURY_CONFIGURATION_SCHEME = “PASSIVE SERIAL”;
FLEX6K_CONFIGURATION_SCHEME = “PASSIVE SERIAL”;
FLEX10K_CONFIGURATION_SCHEME = “PASSIVE SERIAL”;
EXCALIBUR_CONFIGURATION_SCHEME = “PASSIVE SERIAL”;
APEXII_CONFIGURATION_SCHEME = “PASSIVE SERIAL”;
STRATIX_CONFIGURATION_SCHEME = “PASSIVE SERIAL”;
CYCLONE_CONFIGURATION_SCHEME = “ACTIVE SERIAL”;
USE_CONFIGURATION_DEVICE = ON;
APEX20K_CONFIGURATION_DEVICE = AUTO;
MERCURY_CONFIGURATION_DEVICE = AUTO;
FLEX6K_CONFIGURATION_DEVICE = AUTO;
FLEX10K_CONFIGURATION_DEVICE = AUTO;
EXCALIBUR_CONFIGURATION_DEVICE = AUTO;
STRATIX_CONFIGURATION_DEVICE = AUTO;
CYCLONE_CONFIGURATION_DEVICE = AUTO;
STRATIX_UPDATE_MODE = STANDARD;
APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
COMPRESSION_MODE = OFF;
ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
USE_CHECKSUM_AS_USERCODE = OFF;
MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
GENERATE_TTF_FILE = OFF;
GENERATE_RBF_FILE = OFF;
GENERATE_HEX_FILE = OFF;
SECURITY_BIT = OFF;
ENABLE_VREFA_PIN = OFF;
ENABLE_VREFB_PIN = OFF;
GENERATE_SVF_FILE = OFF;
GENERATE_ISC_FILE = OFF;
GENERATE_JAM_FILE = OFF;
GENERATE_JBC_FILE = OFF;
GENERATE_JBC_FILE_COMPRESSED = ON;
GENERATE_CONFIG_SVF_FILE = OFF;
GENERATE_CONFIG_ISC_FILE = OFF;
GENERATE_CONFIG_JAM_FILE = OFF;
GENERATE_CONFIG_JBC_FILE = OFF;
GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
GENERATE_CONFIG_HEXOUT_FILE = OFF;
ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF;
HEXOUT_FILE_START_ADDRESS = 0;
HEXOUT_FILE_COUNT_DIRECTION = UP;
RESERVE_ALL_UNUSED_PINS = “AS INPUT TRI-STATED”;
CLOCK_SOURCE = INTERNAL;
CONFIGURATION_CLOCK_FREQUENCY = “10 MHZ”;
CONFIGURATION_CLOCK_DIVISOR = 1;
RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = “USE AS REGULAR IO”;
RESERVE_RDYNBUSY_AFTER_CONFIGURATION = “USE AS REGULAR IO”;
RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = “USE AS REGULAR IO”;
RESERVE_DATA0_AFTER_CONFIGURATION = “USE AS REGULAR IO”;
RESERVE_NCEO_AFTER_CONFIGURATION = “USE AS REGULAR IO”;
RESERVE_ASDO_AFTER_CONFIGURATION = “USE AS REGULAR IO”;
}

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Quartus Setting File (qsf) of LEON2 on Nios Development (Stratix) board

Posted by mulyanto on April 24, 2007

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation’s design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.

# The default values for assignments are stored in the file
# leon_assignment_defaults.qdf
# If this file doesn’t exist, and for assignments not listed, see file
# assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.

set_global_assignment -name FAMILY STRATIX
set_global_assignment -name DEVICE EP1S40F780C5
set_global_assignment -name TOP_LEVEL_ENTITY leon_stratix
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE “13:00:15 MARCH 24, 2006″
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name VERILOG_FILE verilog\\keyboard\\line_filter.v
set_global_assignment -name VHDL_FILE vhdl\\memory\\sram16_interface.vhd
set_global_assignment -name VHDL_FILE vhdl\\memory\\rom16_interface.vhd
set_global_assignment -name VHDL_FILE vhdl\\vga\\char_rom.vhd
set_global_assignment -name VHDL_FILE vhdl\\vga\\vga_sync.vhd
set_global_assignment -name VHDL_FILE vhdl\\vga\\leon_vga_display.vhd
set_global_assignment -name VHDL_FILE vhdl\\memory\\rom8_interface.vhd
set_global_assignment -name VHDL_FILE vhdl\\memory\\sram8_interface.vhd
set_global_assignment -name VERILOG_FILE verilog\\keyboard\\leon_control.v
set_global_assignment -name VERILOG_FILE verilog\\keyboard\\leon_keyboard_receiver.v
set_global_assignment -name VHDL_FILE ..\\..\\leon\\amba.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\target.vhd
set_global_assignment -name VHDL_FILE device.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\config.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\sparcv8.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\mmuconfig.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\iface.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\apbmst.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\macro.vhd
set_global_assignment -name VHDL_FILE ambacomp.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\bprom.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\multlib.vhd
set_global_assignment -name VHDL_FILE tech_cyclone.vhd
set_global_assignment -name VHDL_FILE tech_stratix.vhd
set_global_assignment -name VHDL_FILE tech_apex20ke.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\tech_generic.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\tech_atc18.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\tech_atc25.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\tech_atc35.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\tech_fs90.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\tech_umc18.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\tech_proasic.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\tech_tsmc25.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\tech_virtex.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\tech_virtex2.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\tech_axcel.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\tech_map.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\dsu.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\dsu_mem.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\ahbmst.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\dcom_uart.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\dcom.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\cachemem.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\icache.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\dcache.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\acache.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\cache.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\rstgen.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\fpulib.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\mul.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\div.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\meiko.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\fpu_lth.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\fpu_core.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\iu.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\proc.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\lconf.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\irqctrl.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\sdmctrl.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\mctrl.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\ioport.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\timers.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\uart.vhd
set_global_assignment -name VHDL_FILE ud_cnt.vhd
set_global_assignment -name VHDL_FILE ro_cnt.vhd
set_global_assignment -name VHDL_FILE atahost_pio_tctrl.vhd
set_global_assignment -name VHDL_FILE atahost_amba_slave.vhd
set_global_assignment -name VHDL_FILE atahost_controller.vhd
set_global_assignment -name VHDL_FILE atahost_top.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\ahbram.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\wprot.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\ahbstat.vhd
set_global_assignment -name VHDL_FILE ..\\..\\leon\\ahbarb.vhd
set_global_assignment -name VHDL_FILE mcore.vhd
set_global_assignment -name VHDL_FILE stratix_board_pll.vhd
set_global_assignment -name VHDL_FILE stratix_board.vhd
set_global_assignment -name VHDL_FILE leon_stratix_lib.vhd
set_global_assignment -name VHDL_FILE leon_stratix.vhd
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name EDA_BOARD_DESIGN_TOOL “”
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL “”
set_global_assignment -name EDA_SIMULATION_TOOL “MODELSIM-ALTERA (VHDL OUTPUT FROM QUARTUS II)”
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL “”
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name DO_MIN_ANALYSIS ON
set_global_assignment -name FMAX_REQUIREMENT “50 MHz”
set_global_assignment -name IGNORE_CLOCK_SETTINGS ON
set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
set_global_assignment -name MAX_SCC_SIZE 50
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE NORMAL
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX NORMAL
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name ACLK_CAT OFF
set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
set_global_assignment -name ASSG_CAT OFF
set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
set_global_assignment -name CLK_CAT OFF
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
set_global_assignment -name CLK_RULE_INV_CLOCK OFF
set_global_assignment -name CLK_RULE_MIX_EDGES OFF
set_global_assignment -name HCPY_CAT OFF
set_global_assignment -name HCPY_VREF_PINS OFF
set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
set_global_assignment -name RESET_CAT OFF
set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
set_global_assignment -name SIGNALRACE_CAT OFF
set_global_assignment -name SIGNALRACE_RULE_TRISTATE OFF
set_global_assignment -name TIMING_CAT OFF
set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
set_global_assignment -name FITTER_EFFORT “STANDARD FIT”
set_global_assignment -name OPTIMIZE_TIMING NORMAL_COMPILATION
set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name EXCALIBUR_CONFIGURATION_DEVICE AUTO
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
set_global_assignment -name RESERVE_PIN “AS INPUT TRI-STATED”
set_location_assignment PIN_K7 -to CF_ATASEL_N
set_location_assignment PIN_H4 -to CF_POWER
set_location_assignment PIN_R3 -to CF_PRESENT_N
set_location_assignment PIN_V25 -to ENET_ADS_N
set_location_assignment PIN_V28 -to ENET_AEN
set_location_assignment PIN_T22 -to ENET_BE_N[0]
set_location_assignment PIN_U26 -to ENET_BE_N[1]
set_location_assignment PIN_U25 -to ENET_BE_N[2]
set_location_assignment PIN_T19 -to ENET_BE_N[3]
set_location_assignment PIN_U27 -to ENET_CYCLE_N
set_location_assignment PIN_T20 -to ENET_DATACS_N
set_location_assignment PIN_V27 -to ENET_INTRQ
set_location_assignment PIN_V26 -to ENET_IOCHRDY
set_location_assignment PIN_T23 -to ENET_IOR_N
set_location_assignment PIN_T24 -to ENET_IOW_N
set_location_assignment PIN_R26 -to ENET_LCLK
set_location_assignment PIN_T26 -to ENET_LDEV_N
set_location_assignment PIN_T28 -to ENET_RDYRTN_N
set_location_assignment PIN_T25 -to ENET_SRDY_N
set_location_assignment PIN_T21 -to ENET_W_R_N
set_location_assignment PIN_K19 -to FLASH_CS_N
set_location_assignment PIN_F19 -to FLASH_OE_N
set_location_assignment PIN_G19 -to FLASH_RW_N
set_location_assignment PIN_A4 -to FSE_A[0]
set_location_assignment PIN_A6 -to FSE_A[10]
set_location_assignment PIN_B7 -to FSE_A[11]
set_location_assignment PIN_D6 -to FSE_A[12]
set_location_assignment PIN_A7 -to FSE_A[13]
set_location_assignment PIN_D7 -to FSE_A[14]
set_location_assignment PIN_C6 -to FSE_A[15]
set_location_assignment PIN_C7 -to FSE_A[16]
set_location_assignment PIN_B6 -to FSE_A[17]
set_location_assignment PIN_D8 -to FSE_A[18]
set_location_assignment PIN_C8 -to FSE_A[19]
set_location_assignment PIN_A3 -to FSE_A[1]
set_location_assignment PIN_E8 -to FSE_A[20]
set_location_assignment PIN_D9 -to FSE_A[21]
set_location_assignment PIN_B9 -to FSE_A[22]
set_location_assignment PIN_B3 -to FSE_A[2]
set_location_assignment PIN_B5 -to FSE_A[3]
set_location_assignment PIN_B4 -to FSE_A[4]
set_location_assignment PIN_C4 -to FSE_A[5]
set_location_assignment PIN_A5 -to FSE_A[6]
set_location_assignment PIN_C5 -to FSE_A[7]
set_location_assignment PIN_D5 -to FSE_A[8]
set_location_assignment PIN_E6 -to FSE_A[9]
set_location_assignment PIN_H12 -to FSE_D[0]
set_location_assignment PIN_A9 -to FSE_D[10]
set_location_assignment PIN_C9 -to FSE_D[11]
set_location_assignment PIN_E10 -to FSE_D[12]
set_location_assignment PIN_A10 -to FSE_D[13]
set_location_assignment PIN_C10 -to FSE_D[14]
set_location_assignment PIN_B10 -to FSE_D[15]
set_location_assignment PIN_A11 -to FSE_D[16]
set_location_assignment PIN_C11 -to FSE_D[17]
set_location_assignment PIN_D11 -to FSE_D[18]
set_location_assignment PIN_B11 -to FSE_D[19]
set_location_assignment PIN_F12 -to FSE_D[1]
set_location_assignment PIN_D10 -to FSE_D[20]
set_location_assignment PIN_G10 -to FSE_D[21]
set_location_assignment PIN_F10 -to FSE_D[22]
set_location_assignment PIN_H11 -to FSE_D[23]
set_location_assignment PIN_G11 -to FSE_D[24]
set_location_assignment PIN_F8 -to FSE_D[25]
set_location_assignment PIN_J9 -to FSE_D[26]
set_location_assignment PIN_J13 -to FSE_D[27]
set_location_assignment PIN_L13 -to FSE_D[28]
set_location_assignment PIN_M11 -to FSE_D[29]
set_location_assignment PIN_J12 -to FSE_D[2]
set_location_assignment PIN_L11 -to FSE_D[30]
set_location_assignment PIN_G7 -to FSE_D[31]
set_location_assignment PIN_M12 -to FSE_D[3]
set_location_assignment PIN_H17 -to FSE_D[4]
set_location_assignment PIN_K18 -to FSE_D[5]
set_location_assignment PIN_H18 -to FSE_D[6]
set_location_assignment PIN_G18 -to FSE_D[7]
set_location_assignment PIN_B8 -to FSE_D[8]
set_location_assignment PIN_A8 -to FSE_D[9]
set_location_assignment PIN_H27 -to LEDG[0]
set_location_assignment PIN_H28 -to LEDG[1]
set_location_assignment PIN_L23 -to LEDG[2]
set_location_assignment PIN_L24 -to LEDG[3]
set_location_assignment PIN_J25 -to LEDG[4]
set_location_assignment PIN_J26 -to LEDG[5]
set_location_assignment PIN_L20 -to LEDG[6]
set_location_assignment PIN_L19 -to LEDG[7]
set_location_assignment PIN_K17 -to PLD_CLOCKINPUT
set_location_assignment PIN_C21 -to PROGMEM[0]
set_location_assignment PIN_B19 -to PROGMEM[10]
set_location_assignment PIN_A19 -to PROGMEM[11]
set_location_assignment PIN_D18 -to PROGMEM[12]
set_location_assignment PIN_C18 -to PROGMEM[13]
set_location_assignment PIN_A18 -to PROGMEM[14]
set_location_assignment PIN_D19 -to PROGMEM[15]
set_location_assignment PIN_B21 -to PROGMEM[1]
set_location_assignment PIN_A21 -to PROGMEM[2]
set_location_assignment PIN_C20 -to PROGMEM[3]
set_location_assignment PIN_A20 -to PROGMEM[4]
set_location_assignment PIN_B20 -to PROGMEM[5]
set_location_assignment PIN_B18 -to PROGMEM[6]
set_location_assignment PIN_D21 -to PROGMEM[7]
set_location_assignment PIN_E19 -to PROGMEM[8]
set_location_assignment PIN_C19 -to PROGMEM[9]
set_location_assignment PIN_Y28 -to RXD1
set_location_assignment PIN_AA28 -to RXD2
set_location_assignment PIN_AE4 -to SDRAM_A[0]
set_location_assignment PIN_Y11 -to SDRAM_A[10]
set_location_assignment PIN_AB7 -to SDRAM_A[11]
set_location_assignment PIN_W12 -to SDRAM_A[1]
set_location_assignment PIN_AC11 -to SDRAM_A[2]
set_location_assignment PIN_W10 -to SDRAM_A[3]
set_location_assignment PIN_AA11 -to SDRAM_A[4]
set_location_assignment PIN_AC10 -to SDRAM_A[5]
set_location_assignment PIN_AB11 -to SDRAM_A[6]
set_location_assignment PIN_AC8 -to SDRAM_A[7]
set_location_assignment PIN_AB10 -to SDRAM_A[8]
set_location_assignment PIN_V11 -to SDRAM_A[9]
set_location_assignment PIN_AG19 -to SDRAM_BA[0]
set_location_assignment PIN_AF19 -to SDRAM_BA[1]
set_location_assignment PIN_AD18 -to SDRAM_CAS_N
set_location_assignment PIN_AE18 -to SDRAM_CKE
set_location_assignment PIN_E15 -to SDRAM_CLK
set_location_assignment PIN_AG18 -to SDRAM_CS_N
set_location_assignment PIN_AE14 -to SDRAM_DQM[0]
set_location_assignment PIN_Y13 -to SDRAM_DQM[1]
set_location_assignment PIN_AE7 -to SDRAM_DQM[2]
set_location_assignment PIN_AG10 -to SDRAM_DQM[3]
set_location_assignment PIN_AH4 -to SDRAM_DQ[0]
set_location_assignment PIN_AH6 -to SDRAM_DQ[10]
set_location_assignment PIN_AD6 -to SDRAM_DQ[11]
set_location_assignment PIN_AF7 -to SDRAM_DQ[12]
set_location_assignment PIN_AH7 -to SDRAM_DQ[13]
set_location_assignment PIN_AG7 -to SDRAM_DQ[14]
set_location_assignment PIN_AF6 -to SDRAM_DQ[15]
set_location_assignment PIN_AG8 -to SDRAM_DQ[16]
set_location_assignment PIN_AF8 -to SDRAM_DQ[17]
set_location_assignment PIN_AD8 -to SDRAM_DQ[18]
set_location_assignment PIN_AH9 -to SDRAM_DQ[19]
set_location_assignment PIN_AE5 -to SDRAM_DQ[1]
set_location_assignment PIN_AH8 -to SDRAM_DQ[20]
set_location_assignment PIN_AE9 -to SDRAM_DQ[21]
set_location_assignment PIN_AF9 -to SDRAM_DQ[22]
set_location_assignment PIN_AG9 -to SDRAM_DQ[23]
set_location_assignment PIN_AD10 -to SDRAM_DQ[24]
set_location_assignment PIN_AF10 -to SDRAM_DQ[25]
set_location_assignment PIN_AH10 -to SDRAM_DQ[26]
set_location_assignment PIN_AE10 -to SDRAM_DQ[27]
set_location_assignment PIN_AF11 -to SDRAM_DQ[28]
set_location_assignment PIN_AE11 -to SDRAM_DQ[29]
set_location_assignment PIN_AG3 -to SDRAM_DQ[2]
set_location_assignment PIN_AH11 -to SDRAM_DQ[30]
set_location_assignment PIN_AG11 -to SDRAM_DQ[31]
set_location_assignment PIN_AG5 -to SDRAM_DQ[3]
set_location_assignment PIN_AG4 -to SDRAM_DQ[4]
set_location_assignment PIN_AF4 -to SDRAM_DQ[5]
set_location_assignment PIN_AH5 -to SDRAM_DQ[6]
set_location_assignment PIN_AF5 -to SDRAM_DQ[7]
set_location_assignment PIN_AE6 -to SDRAM_DQ[8]
set_location_assignment PIN_AG6 -to SDRAM_DQ[9]
set_location_assignment PIN_AH3 -to SDRAM_RAS_N
set_location_assignment PIN_AH19 -to SDRAM_WE_N
set_location_assignment PIN_M18 -to SRAM_BE_N[0]
set_location_assignment PIN_F17 -to SRAM_BE_N[1]
set_location_assignment PIN_J18 -to SRAM_BE_N[2]
set_location_assignment PIN_L17 -to SRAM_BE_N[3]
set_location_assignment PIN_B24 -to SRAM_CS_N
set_location_assignment PIN_B26 -to SRAM_OE_N
set_location_assignment PIN_C24 -to SRAM_WE_N
set_location_assignment PIN_U21 -to TXD1
set_location_assignment PIN_V24 -to TXD2
set_location_assignment PIN_AB2 -to USER_PB1[0]
set_location_assignment PIN_AB1 -to USER_PB1[1]
set_location_assignment PIN_W5 -to USER_PB[0]
set_location_assignment PIN_W6 -to USER_PB[1]
set_location_assignment PIN_M5 -to cf_ide_INTRQ
set_location_assignment PIN_K1 -to cf_ide_IORDY
set_location_assignment PIN_M9 -to cf_ide_IORDn
set_location_assignment PIN_AG24 -to cf_ide_IOSn
set_location_assignment PIN_M10 -to cf_ide_IOWRn
set_location_assignment PIN_L9 -to cf_ide_a[0]
set_location_assignment PIN_M7 -to cf_ide_a[10]
set_location_assignment PIN_J3 -to cf_ide_a[1]
set_location_assignment PIN_L10 -to cf_ide_a[2]
set_location_assignment PIN_L6 -to cf_ide_a[3]
set_location_assignment PIN_H1 -to cf_ide_a[4]
set_location_assignment PIN_H2 -to cf_ide_a[5]
set_location_assignment PIN_L8 -to cf_ide_a[6]
set_location_assignment PIN_L7 -to cf_ide_a[7]
set_location_assignment PIN_H3 -to cf_ide_a[8]
set_location_assignment PIN_K3 -to cf_ide_a[9]
set_location_assignment PIN_J2 -to cf_ide_cs0n
set_location_assignment PIN_K8 -to cf_ide_cs1n
set_location_assignment PIN_K2 -to cf_ide_csel
set_location_assignment PIN_AD23 -to cf_ide_dasp
set_location_assignment PIN_N3 -to cf_ide_data[0]
set_location_assignment PIN_N5 -to cf_ide_data[10]
set_location_assignment PIN_M3 -to cf_ide_data[11]
set_location_assignment PIN_N7 -to cf_ide_data[12]
set_location_assignment PIN_L1 -to cf_ide_data[13]
set_location_assignment PIN_N4 -to cf_ide_data[14]
set_location_assignment PIN_L3 -to cf_ide_data[15]
set_location_assignment PIN_L2 -to cf_ide_data[1]
set_location_assignment PIN_N8 -to cf_ide_data[2]
set_location_assignment PIN_M4 -to cf_ide_data[3]
set_location_assignment PIN_N6 -to cf_ide_data[4]
set_location_assignment PIN_N1 -to cf_ide_data[5]
set_location_assignment PIN_N9 -to cf_ide_data[6]
set_location_assignment PIN_P3 -to cf_ide_data[7]
set_location_assignment PIN_N10 -to cf_ide_data[8]
set_location_assignment PIN_M2 -to cf_ide_data[9]
set_location_assignment PIN_J4 -to cf_ide_inpack
set_location_assignment PIN_M8 -to cf_ide_pdiag
set_location_assignment PIN_V18 -to cf_ide_reg
set_location_assignment PIN_L5 -to cf_ide_we
set_global_assignment -name RESERVE_ALL_UNUSED_PINS “AS INPUT TRI-STATED”
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION “USE AS REGULAR IO”
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND “AS INPUT TRI-STATED”

Posted in Altera, Embedded System | Leave a Comment »

Top level of LEON2 on Nios Development (Stratix) board

Posted by mulyanto on April 24, 2007

—————————————————————————-
– This file is a part of the LEON VHDL model
– Copyright (C) 1999 European Space Agency (ESA)

– This library is free software; you can redistribute it and/or
– modify it under the terms of the GNU Lesser General Public
– License as published by the Free Software Foundation; either
– version 2 of the License, or (at your option) any later version.

– See the file COPYING.LGPL for the full details of the license.

—————————————————————————–
– Entity: leon_stratix
– File: leon_top.vhd
– Author: Jiri Gaisler
– Author: Tom Tierens – De Nayer Instituut
– E-mail: tomtierens@yahoo.com
– Author: Denny Tresna S – Bandung Institute of Technology
– Author: Akhmad Mulyanto – Institut Teknologi Bandung
– E-mail: akhmadm@yahoo.com
– Description: Complete processor
——————————————————————————

library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.tech_map.all;
use work.leon_stratix_lib.all;
– pragma translate_off
use work.debug.all;
– pragma translate_on

entity leon_stratix is
port (
— general
PLD_CLOCKINPUT : in std_logic;

– debugging UART
TXD1 : out std_logic;
RXD1 : in std_logic;
TXD2 : out std_logic;
RXD2 : in std_logic;

–resetn : in std_logic;
LEDG : out std_logic_vector(7 downto 0);
USER_PB : in std_logic_vector(1 downto 0);
USER_PB1 : inout std_logic_vector(1 downto 0);

FSE_A : out std_logic_vector(22 downto 0); – memory bus
FSE_D : inout std_logic_vector(31 downto 0);

– flash
FLASH_CS_N : out std_logic;
FLASH_OE_N : out std_logic;
FLASH_RW_N : out std_logic;
–FLASH_RY_BY_N : in std_logic;

– sram
SRAM_BE_N : out std_logic_vector(3 downto 0);
SRAM_CS_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_WE_N : inout std_logic;

– sdram i/f
SDRAM_DQ : inout std_logic_vector(31 downto 0);
SDRAM_A : out std_logic_vector(11 downto 0);

SDRAM_CKE : out std_logic; — clk en
SDRAM_CS_N : out std_logic; — chip sel
SDRAM_WE_N : out std_logic; — write en
SDRAM_RAS_N : out std_logic; — row addr stb
SDRAM_CAS_N : out std_logic; — col addr stb
SDRAM_DQM : out std_logic_vector(3 downto 0); — data i/o mask
SDRAM_BA : out std_logic_vector(1 downto 0); — bank select
SDRAM_CLK : out std_logic; — sdram clk output

– compactflash signals
cf_ide_a : out std_logic_vector(10 downto 0);
cf_ide_pdiag : inout std_logic;
cf_ide_dasp : inout std_logic;
CF_PRESENT_N : in std_logic;
cf_ide_cs0n : out std_logic;
cf_ide_cs1n : out std_logic;
cf_ide_csel : out std_logic;
cf_ide_data : inout std_logic_vector(15 downto 0);
cf_ide_inpack : in std_logic;
cf_ide_IORDn : out std_logic;
cf_ide_IOWRn : out std_logic;
CF_ATASEL_N : out std_logic;
cf_ide_INTRQ : in std_logic;
cf_ide_reg : out std_logic;
cf_ide_IORDY : in std_logic;
cf_ide_we : out std_logic;
cf_ide_IOSn : in std_logic;

CF_POWER : out std_logic;
–cf_ide_dmack_n : out std_logic;

ENET_BE_N : out std_logic_vector(3 downto 0);
ENET_AEN : out std_logic;
ENET_ADS_N : out std_logic;
ENET_LCLK : out std_logic;
ENET_IOCHRDY : in std_logic;
ENET_RDYRTN_N : out std_logic;
ENET_SRDY_N : in std_logic;
ENET_INTRQ : in std_logic;
ENET_LDEV_N : in std_logic;
ENET_IOR_N : out std_logic;
ENET_IOW_N : out std_logic;
ENET_DATACS_N : out std_logic;
ENET_CYCLE_N : out std_logic;
ENET_W_R_N : out std_logic;

–codec core
PROGMEM : out std_logic_vector(15 downto 0));

end;

architecture rtl of leon_stratix is

– general
signal gnd, vcc, clko, sdclkl, resetno : std_logic;
signal clkm, clkn, pciclk : clk_type;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal ioi : io_in_type;
signal ioo : io_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal dsi : dsuif_in_type;
signal dso : dsuif_out_type;
signal sdo : sdram_out_type;
signal pllref : clk_type;
signal pllctrl : std_logic_vector(1 downto 0);
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;

– signal pio : std_logic_vector(15 downto 0); – I/O port
signal test : std_logic;
signal wdogn : std_logic;

signal clock25 : std_logic;

signal uart1rxd : std_logic;
signal uart1txd : std_logic;

signal dsuen : std_logic;
signal dsuen_toggle : std_logic;
signal dsuen_toggle_out : std_logic;

– ide signals
signal ocideci : ocide_in_type;
signal ocideco : ocide_out_type;

– lan 91c111 chip
signal enet_irq : std_logic;
signal nWR : std_logic;
signal nRD : std_logic;
signal wait_one_clock : std_logic;
signal extend_enet_access : std_logic;
signal inversed_datai : std_logic_vector(31 downto 0);
signal inversed_datao : std_logic_vector(31 downto 0);
signal flash_datai : std_logic_vector(31 downto 0);
signal flash_datao : std_logic_vector(31 downto 0);
signal enet_ben : std_logic_vector(3 downto 0);
signal ram_ben : std_logic_vector(3 downto 0);
signal enetaen : std_logic;
signal extend_ben : std_logic_vector(3 downto 0);
signal extend_oen : std_logic;
signal enet_address : std_logic_vector(2 downto 0);

–signal pio_i : std_logic;
–attribute keep_hierarchy : String;
–attribute keep_hierarchy of rtl : architecture is “yes”;

begin

– port maps
— general
gnd resetno, clk => clkm, clkn => clkn, pciclk => pciclk,
memi => memi, memo => memo, ioi => ioi, ioo => ioo,
pcii => pcii, pcio => pcio, dsi => dsi, dso => dso, sdo => sdo,
ethi => ethi, etho => etho, cgo => cgo, test => test,
ocideci => ocideci, ocideco => ocideco, enet_irq => enet_irq,
uart1rxd => uart1rxd, uart1txd => uart1txd
);

cgi.pllctrl PLD_CLOCKINPUT,
out_clk => clock25
);

clko clock25, key => dsuen, pulse => dsuen_toggle);
dsuen_toggleflipflop0 : toggleflipflop
port map ( t => dsuen_toggle, clk => clock25, q => dsuen_toggle_out , qn => open );
dsi.dsui.dsuen

Posted in Altera, Embedded System | Leave a Comment »

Using Leon

Posted by mulyanto on April 19, 2007

For example, the top level directory is:

$ C:\Cygwin\home\mul\leon2-1.0.32-internal-stratix

The top level directory contains:

$ C:\Cygwin\home\mul\leon2-1.0.32-internal-stratix\doc –> documentation files
$ C:\Cygwin\home\mul\leon2-1.0.32-internal-stratix\leon –> design files
$ C:\Cygwin\home\mul\leon2-1.0.32-internal-stratix\literature –> Literature files
$ C:\Cygwin\home\mul\leon2-1.0.32-internal-stratix\pmon –>
$ C:\Cygwin\home\mul\leon2-1.0.32-internal-stratix\sim –> Simulation directory
$ C:\Cygwin\home\mul\leon2-1.0.32-internal-stratix\soft –> Software files
$ C:\Cygwin\home\mul\leon2-1.0.32-internal-stratix\syn –> Synthesis directory
$ C:\Cygwin\home\mul\leon2-1.0.32-internal-stratix\tbench –> Testbench files
$ C:\Cygwin\home\mul\leon2-1.0.32-internal-stratix\tkconfig –>
$ C:\Cygwin\home\mul\leon2-1.0.32-internal-stratix\tsource –>

First, configure Leon :

On $ C:\Cygwin\home\mul\leon2-1.0.32-internal-stratix do :

$ make xconfig

After configuration finished , compile and download LEON on the FPGA.

Go to $ C:\Cygwin\home\mul\leon2-1.0.32-internal-stratix\soft, do :

$ dsumon

if you are only have one RS232 cable you must be use dsumon in loop mode:

$ dsumon -u

In order to make dsumon working properly, you have add C:\Cygwin\home\mul\opt\rtems\bin in the path of system variable

You can force LEON to ready for data transfer using comand:

$ dsumon -i -u

or if you want to download the programming file hello.exe:

$ dsumon -i -u hello.exe

Posted in Embedded System, Tutorial | Leave a Comment »