Information on LEON3 Simulation

http://tech.groups.yahoo.com/group/leon_sparc/message/12106

Re: [leon_sparc] Running test program on leon in modelsim

You do not want to simulate a mkprom image in VHDL, trust me.
Even the smallest image will execute ~ 1,000,000 instructions
before entering main() in RAM. This is only ~ 30 ms on real
hardware at 50 MHz, but ~ 10 hours in VHDL (on a fast host).

You can easily see in TSIM how many instructions you will need:

sparc-elf-gcc -msoft-float hello.c -o hello.exe -lsmall
sparc-elf-mkprom hello.exe -nocomp -nomsg

tsim-leon3 prom.out
.
.
section: .text, addr: 0×0, size 34304 bytes
read 103 symbols
tsim> bre 0×40000000
breakpoint 1 at 0×40000000: .bdata
tsim> run
breakpoint 1 .bdata
tsim> per

Cycles : 1399497
Instructions : 906783
Overall CPI : 1.54

CPU performance (50.0 MHz) : 32.40 MOPS (32.40 MIPS, 0.00 MFLOPS)
Cache hit rate : 98.7 % (100.0 / 80.0)
AHB bandwidth utilisation : 33.7 % ( 0.4 / 33.3)
Simulated time : 27.99 ms
Processor utilisation : 100.00 %
Real-time performance : 11.86 %
Simulator performance : 3843.69 KIPS
Used time (sys + user) : 0.24 s

So even if we created the smallest possible binary using -lsmall
and fastest mkprom loading with -nomsg and -nocomp, you will need
to execute 906,783 instructions to get to RAM, and then maybe an
other 10,000 to get to main(). This is why the test bench in leon3
designs does NOT use mkprom, but a simple assembly reset sequence
and a pre-loaded RAM image…

Jiri.

sacliv wrote:
> Hey guys, I’m trying to load a test c program i wrote on the leon3 in
> the vhdl leon3 code and run it in modelsim to view the waveforms.
>
> I followed the bcc manual and did mkprom on my executable, and then i
> copied the .srec file to the testbench directory, and in the
> testbench.vhd, i changed the filename of the prom.srec to test.srec,
> which is my srec file.
>
> The test program is very simple and just prints out hello world, but
> in the modelsim simulation of the leon3, i’m watching the pc and
> instructions of the leon3 core, but i can’t seem to get to my test
> program.
>
> Does anyone know either how long i have to simulate it until before i
> get to main() in my test program? Or if i’m doing it wrong, what’s the
> correct procedure? Thanks!

================================================================================================
http://tech.groups.yahoo.com/group/leon_sparc/message/12108

Re: [leon_sparc] Re: Running test program on leon in modelsim

See how the test bench is compiled by doing ‘make soft’ in the
template design directory. The final command will be:

sparc-elf-gcc -I../../software/leon3 -O2 -g -msoft-float systest.c -L./
lib3tests.a -o systest.exe
sparc-elf-objcopy -O srec systest.exe sram.srec

You can do pretty much the same using your own application:

sparc-elf-gcc -O2 -g -msoft-float myapp.c -o myapp.exe
sparc-elf-objcopy -O srec myapp.exe sram.srec

And make sure you understand how to use the ‘volatile’ keyword
in C if you intend to do any memory tests or similar …

Jiri.

sacliv wrote:
> Wow that’s good to know. So is there a way to easily simulate my test
> code using the leon3 VHDL code?

================================================================================================

http://tech.groups.yahoo.com/group/leon_sparc/message/12114

Re: [leon_sparc] Re: Running test program on leon in modelsim

You can run your code from PROM for fastest run-time. Copy prom.S
from software/leon3 to you local template design, and do ‘make soft’.
Then, add your instructions just before the code jumps to RAM at
the end of the file:

set RAMSTART, %g1
<–insert here
jmp %g1
nop

Do a ‘make soft’ again, and restart simulation. Note that you can
get assembly output from the simulation by setting the disas generic
to 1 (or start modelsim with -gdisas=1) .

Jiri.

================================================================================================

http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=92&Itemid=66

How do I put the content of a file “as is” into the .data section (or somewhere else into memory)?
You can add a binary file to an existing elf file with objcopy, by adding a new section and fill it with the desired content:

sparc-elf-objcopy –add-section .myelfsection=file.bin –change-section-address .myelfsection=0×00001000

–set-section-flags .myelfsection=alloc,contents,load,data file.exe

The example above adds the file ‘file.bin’ to the elf file ‘file.exe’ at address 0×1000. Note that this is done after linking.

================================================================================================

Design Examples For Altera Terasic DE2 Board

Here is the project :

http://www.geocities.com/akhmadm/hdl_design/DE2_sunset.zip

The design is very simple, only viewing a image (sunset) that saved in 3 ROM.
Use Matlab to convert the image to text files.
Use tb_de2.v to covert text files to Altera mif file (click the the de2.mpf to open Modelsim, then execute script compile.do.
Change the mif file to hex file using quartus editor or quartus tool (open mif file then save as hex file).
You can use the altera_rom function for another design.

Verilog task for loading text file to registers

CODE :

integer data [255:0];

task read_file;
input integer i_infile;
input integer numdata;
input integer indeks_init;
input reg [7:0] file_type;
input display_testvector;

integer indeks;
integer kolom,baris;
integer i_c,i_r,i;

reg file_opened,file_closed;

begin
//$display("============= %s ======================",file_type);
file_opened = 1'b0;
file_closed = 1'b0;
i_c = 0;
i_r = 0;
indeks = indeks_init;

for(i=0; i<(numdata); i=i+1)
begin
data[i] = 0;
end

if (i_infile ==0) // If error opening file
begin
$display("File input not found !!!!!!!");
disable file_input_block; // Just quit
end
else
begin
file_opened = 1'b1;
end

if (~file_closed & file_opened)
begin
i_c = $fgetc(i_infile);
//$display("%8x", i_c);
while (i_c != `EOF)//
begin
if (i_c == "/")
begin
i_r = $ungetc(i_c, i_infile);
//$display("COMMENT");
i_c = $fgets(line, i_infile); // Read the comment
if (display_testvector == 1'b1)
begin
$display("%s", line);
end
end
else
begin

i_r = $ungetc(i_c, i_infile); // PuSH char back
if(file_type=="h") begin
i_c = $fscanf(i_infile,"%x",data[indeks]);
end else begin
i_c = $fscanf(i_infile,"%d",data[indeks]);
end

if (display_testvector == 1'b1)
begin
$display(" data[%8d] = %8x",indeks,data[indeks]);
end
indeks = indeks + 1;
end

i_c = $fgetc(i_infile);
//$display("%8x", i_c);
if(indeks==numdata)
begin
i_c = `EOF;
end

end
$fclose(i_infile);
file_closed = 1'b1;
end
end
endtask

HOW TO USE THE TASK :

1. Add task read_file in your verilog tesbench.
2. Call the task, example:


integer i_infile;

initial
begin : file_input_block
starter = 1'b0;
//----------------------------------------
//read file test vector test_in.txt
//----------------------------------------
i_infile1 = $fopen("./testvector/test_in.txt", "r");
read_file(i_infile1,256,1,"d",0);
for(i=0; i<(256); i=i+1) begin
regfile[i] = data[i];
end

//starting the test
starter = 1'b1;

dut dut_inst (
.clk (clk)
,.addr (addr)
,.datain (regfile[addr])
);

end


ModelSim Script for Altera Simulation

transcript on
if ![file isdirectory verilog_libs] {
file mkdir verilog_libs
}

vlib verilog_libs/stratixii_ver
vmap stratixii_ver verilog_libs/stratixii_ver
vlog -work stratixii_ver c:/altera/quartus60/eda/sim_lib/stratixii_atoms.v

vlib verilog_libs/lpm_ver
vmap lpm_ver verilog_libs/lpm_ver
vlog -work lpm_ver c:/altera/quartus60/eda/sim_lib/220model.v

vlib verilog_libs/altera_ver
vmap altera_ver verilog_libs/altera_ver
vlog -work altera_ver c:/altera/quartus60/eda/sim_lib/altera_primitives.v

vlib verilog_libs/altera_mf_ver
vmap altera_mf_ver verilog_libs/altera_mf_ver
vlog -work altera_mf_ver c:/altera/quartus60/eda/sim_lib/altera_mf.v

vlib verilog_libs/sgate_ver
vmap sgate_ver verilog_libs/sgate_ver
vlog -work sgate_ver c:/altera/quartus60/eda/sim_lib/sgate.v

if {[file exists rtl_work]} {
vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

vlog -work rtl_work ./rtl/cordic-mul/add_sub.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/cordic-mul/unsign.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/cordic-mul/dff_acc.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/cordic-mul/dffen_acc.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/cordic-mul/angle_rom.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/cordic-mul/iterator_ctrl.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/cordic-mul/iterator.v +incdir+./rtl +define+SIM

vlog -work rtl_work ./rtl/negator.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/extender.v +incdir+./rtl +define+SIM
vlog -work rtl_work -L lpm_ver ./fpga/rtl/add_sub19.v
vlog -work rtl_work -L lpm_ver ./fpga/rtl/add_sub22.v
vlog -work rtl_work -L altera_mf_ver ./fpga/rtl/angle1.v
vlog -work rtl_work ./rtl/cordic-mul-2/iterator_ctrl1.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/cordic-mul-2/iterator_ctrl1p.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/cordic-mul-2/iterator1.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/cordic-mul-2/iterator1p.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/cordic-mul-2/cordic_mul.v +incdir+./rtl +define+SIM

vlog -work rtl_work ./rtl/parallel-divider/casblock32p.v +incdir+./rtl +incdir+./rtl/parallel-divider +define+SIM
vlog -work rtl_work ./rtl/parallel-divider/divider32.v +incdir+./rtl +incdir+./rtl/parallel-divider +define+SIM

vlog -work rtl_work ./rtl/parallel-divider/casblockparameterized.v +incdir+./rtl +incdir+./rtl/parallel-divider +define+SIM
vlog -work rtl_work ./rtl/parallel-divider/divider_parameterized.v +incdir+./rtl +incdir+./rtl/parallel-divider +define+SIM

vlog -work rtl_work ./rtl/pipe_mxn.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/pipe_mx1.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/hls.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/est_ctrl.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/estimator_top.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/registers.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/eq_div.v +incdir+./rtl +define+SIM
vlog -work rtl_work -L lpm_ver ./fpga/rtl/divider32sign_1clk.v
vlog -work rtl_work -L lpm_ver ./rtl/eq_divp1.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/eq_div_lpm.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/averager.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/r_proc.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/theta_proc.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/ram_sel.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/data_sel.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/theta_neg.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/eq_ctrl.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/ram_output.v +incdir+./rtl +define+SIM
vlog -work rtl_work ./rtl/equalizer.v +incdir+./rtl +define+SIM

vlog -work rtl_work ./testbench/functions_lib.v +incdir+./testbench +incdir+./rtl
vlog -work rtl_work ./testbench/task_lib.v +incdir+./testbench +incdir+./rtl
vlog -work rtl_work ./testbench/tb_equalizer.v +incdir+./testbench +incdir+./rtl

vsim -t 1ps -L rtl_work -L lpm_ver -L altera_mf_ver tb_equalizer

Passing parameter value from do file to verilog

Here is part of tesbench for divider exhaustive test.


initial begin // Exhaustive patterns
#delay_for_exhaustive_patterns
word_dividend = `START_NUM;
while (word_dividend <= `END_NUM)
begin
word_divisor = 1;
while (word_divisor <= `MAX_DIVISOR) begin
#0 Start = 0;
#start_offset Start = 1;
#start_duration Start = 0;
@ (posedge Ready)
#0;
word_divisor = word_divisor + 1;
end // divisor pattern
word_dividend = word_dividend + 1;
end // dividend pattern
$stop;
end


If you want test in an automatic multiple test with separate log file, then we need pass some paramater value and some file name from do file to verilog.

Here is the example of the do file :

vlog ./rtl/Dividers/Divider_STG_0.v +incdir+./rtl
#vlog ./rtl/Dividers/Divider_STG_1.v +incdir+./rtl
#vlog ./rtl/Dividers/Divider_STG_0_sub.v +incdir+./rtl
vlog ./rtl/Dividers/Divider_RR_STG.v +incdir+./rtl/Dividers

exec start_time.exe
set ontest 1
set numtest 1

while {$ontest} {
set out [open namefile.txt w]
scan $numtest "%4x" filename
puts $out [format "test%4x.txt" $filename ]
close $out
vlog ./rtl/Dividers/t_Divider_RR_STG.v +incdir+./rtl/Dividers +define+START_NUM=$numtest +define+END_NUM=8'hFF +define+namefile=$numtest
vsim test_Divider_RR_STG
run -all
incr numtest
if {$numtest == 256} {set ontest 0}
}

exec end_time.exe
exec playing_sound.exe

the comand :

set out [open namefile.txt w]
scan $numtest "%4x" filename
puts $out [format "test%4x.txt" $filename ]
close $out



convert numtest to string and save it in namefile.txt. Verilog tesbench then read namefile.txt and use the contain of namefile.txt as log file name. Here is the verilog code :


initial

begin : log_file

dumpfile1 = $fopen("namefile.txt", "r");
i_c = $fgets(indeks, dumpfile1);
$display("hallo%s",indeks);
$fclose(dumpfile1);

end

always @ (posedge quotient_error or posedge rem_error or posedge reset) begin
if(reset) begin
cnt_quot_error <= 16'd0;
cnt_rem_error <= 16'd0;
end
else if(quotient_error | rem_error) begin
dumpfile2 = $fopen(indeks, "w");
if(quotient_error) begin
cnt_quot_error <= cnt_quot_error + 16'd1;
$fdisplay(dumpfile2,"quot= %14x %14x exp_quot error ",quotient,expected_quotient,cnt_quot_error);
end
if(rem_error) begin
cnt_rem_error <= cnt_rem_error + 16'd1;
$fdisplay(dumpfile2,"rem= %14x %14x exp_rem error",remainder,expected_remainder,cnt_rem_error);
end
$fclose(dumpfile2);
end

end

Integer to String and String Concatenation in VHDL

First, make a library called vsilicon (you can use another name). This library constructed from modelsims textio.vhd. The textio.vhd modified and renamed as textio_vs.vhd in order to avoid library error. The Int_to_string procedure/function in textio.vhd also renamed as Int_to_string_vs in textio_vs.vhd. All constant/subtype/variable also renamed for the similar reason. Here is the textio_vs.vhd.(textio_vs.pdf)

on your modelsim prompt, type:

vlib vsilicon
vcom -93 -work vsilicon ../../lib/vsilicon/sim/TEXTIO_VS.vhd

Put the library on your tesbench/design

library vsilicon;
use vsilicon.TextIO_VS.all;

Now you can call Int_to_string_vs function in your tesbench/design.

Example:

verilog_parameter_interface : process
file WFile: Text;
variable LW: Line;
variable IW: integer;
variable last: integer;
variable SW: string(1 to 22);
variable CW: string(1 to 2);
variable NW: string(1 to 20);
variable first : integer := 1;

begin

if (first = 1) then
File_Open(WFile, “leon3parameters.v”, Write_Mode);

CW := Int_to_string_vs(romwidth);
NW := “`define romwidth “;
SW := NW & CW;
WRITE(LW, SW);
WriteLine(WFile, LW);

CW := Int_to_string_vs(romdepth);
NW := “`define romdepth “;
SW := NW & CW;
WRITE(LW, SW);
WriteLine(WFile, LW);

CW := Int_to_string_vs(sramwidth);
NW := “`define sramwidth “;
SW := NW & CW;
WRITE(LW, SW);
WriteLine(WFile, LW);

CW := Int_to_string_vs(sramdepth);
NW := “`define sramdepth “;
SW := NW & CW;
WRITE(LW, SW);
WriteLine(WFile, LW);

File_Close(WFile);
first := 0;
end if;
wait;
end process;

Running Executable File In Modelsim Environment

Have you ever running Modelsim simulation for hours? a day? or more?
You don’t know exactly when the simulation will be finished, and you want to know exactly how long the simulation take time.

First you have to write c-code to generate start_time.exe. The start_time.exe is a simple DOS application. A single executable file. Put the start_time.exe in your modelsim working directory. Download the visual-c 6.0 project fror start_time here.

Add in your script (in the start of script):

exec start_time.exe

Then you have to write c-code to generate stop_time.exe. Download the visual-c 6.0 project fror end_time here
Add in your script (in the end of script):

exec stop_time.exe

Finally if you busy doing something else while you waiting the simulation finish, you can add in your script a command to playing sound that indicated the simulation finished. Download the visual-c 6.0 project fror playing_sound here

exec playing_sound.exe

Here is the example of the script:

#get the start time
exec start_time.exe

#compile the design files
vcom -work work ../VHDL/Tools/images.vhd
vcom -work work ../VHDL/Tools/images-body.vhd
vcom -work work ../VHDL/Tools/textfunc.vhd
vcom -work work ../VHDL/Packages/sys_std.vhd
vcom -work work ../VHDL/Registers/reg16.vhd
….
vcom -work work ../VHDL/CoDec_Core/ME/me_sys_tb.vhd

#simulate the design
vsim work.me_sys_tb
destroy .structure
view structure
view signals
add wave -format Default -radix symbolic sim:/me_sys_tb/current_state
add wave -format Default -radix symbolic sim:/me_sys_tb/hp_run
add wave -format Default -radix symbolic sim:/me_sys_tb/start_hp
add wave -format Default -radix symbolic sim:/me_sys_tb/end_hp

#setup modelsim preference
do modelsim.tcl
restart -f

#runing the simulation
run 180000 ns

#get the stop time
exec end_time.exe

#display end of simulation message
echo “@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@”
echo “@@@@@@@@@@@@@@@@———-End of Simulation——@@@@@@@@@@@@@@@@”
echo “@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@”

#play the sound
exec playing_sound.exe

So you can make mpeg player, mp3 player or else in verilog/modelsim. You need to make an interface that convert video/compressed into text file for verilog/vhdl design. Then you need to make another interface that convert the text file generated by verilog/vhdl design into video/compressed file for mpeg player or mp3 player.

Making SIMPRIM Library for Modelsim

In order to run the Xilinx post-layout model simulation properly, your Modelsim must have a SIMPRIM library. If your Modelsim does not have it, follow the instruction below:

1. Open Modelsim
2. Change directory to C:\Modeltech_6.0
3. Run the script below:

set xilinx_src “C:/Xilinx/verilog/src”

vlib simprims_ver

vlog -work simprims_ver $xilinx_src/glbl.v
vlog -work simprims_ver $xilinx_src/simprims/X_ZERO.v
vlog -work simprims_ver $xilinx_src/simprims/X_AFIFO36_INTERNAL.v
vlog -work simprims_ver $xilinx_src/simprims/X_AND2.v
vlog -work simprims_ver $xilinx_src/simprims/X_AND3.v
vlog -work simprims_ver $xilinx_src/simprims/X_AND4.v
vlog -work simprims_ver $xilinx_src/simprims/X_AND5.v
vlog -work simprims_ver $xilinx_src/simprims/X_AND6.v
vlog -work simprims_ver $xilinx_src/simprims/X_AND7.v
vlog -work simprims_ver $xilinx_src/simprims/X_AND8.v
vlog -work simprims_ver $xilinx_src/simprims/X_AND9.v
vlog -work simprims_ver $xilinx_src/simprims/X_AND16.v
vlog -work simprims_ver $xilinx_src/simprims/X_AND32.v
vlog -work simprims_ver $xilinx_src/simprims/X_ARAMB36_INTERNAL.v
vlog -work simprims_ver $xilinx_src/simprims/X_BPAD.v
vlog -work simprims_ver $xilinx_src/simprims/X_BSCAN_FPGACORE.v
vlog -work simprims_ver $xilinx_src/simprims/X_BSCAN_SPARTAN2.v
vlog -work simprims_ver $xilinx_src/simprims/X_BSCAN_SPARTAN3.v
vlog -work simprims_ver $xilinx_src/simprims/X_BSCAN_VIRTEX2.v
vlog -work simprims_ver $xilinx_src/simprims/X_BSCAN_VIRTEX4.v
vlog -work simprims_ver $xilinx_src/simprims/X_BSCAN_VIRTEX5.v
vlog -work simprims_ver $xilinx_src/simprims/X_BSCAN_VIRTEX.v
vlog -work simprims_ver $xilinx_src/simprims/X_BUF.v
vlog -work simprims_ver $xilinx_src/simprims/X_BUFGCTRL.v
vlog -work simprims_ver $xilinx_src/simprims/X_BUFGMUX.v
vlog -work simprims_ver $xilinx_src/simprims/X_BUFGMUX_1.v
vlog -work simprims_ver $xilinx_src/simprims/X_BUFR.v
vlog -work simprims_ver $xilinx_src/simprims/X_CARRY4.v
vlog -work simprims_ver $xilinx_src/simprims/X_CKBUF.v
vlog -work simprims_ver $xilinx_src/simprims/X_CLK_DIV.v
vlog -work simprims_ver $xilinx_src/simprims/X_CLKDLL.v
vlog -work simprims_ver $xilinx_src/simprims/X_CLKDLLE.v
vlog -work simprims_ver $xilinx_src/simprims/X_CRC32.v
vlog -work simprims_ver $xilinx_src/simprims/X_CRC64.v
vlog -work simprims_ver $xilinx_src/simprims/X_DCM.v
vlog -work simprims_ver $xilinx_src/simprims/X_DCM_ADV.v
vlog -work simprims_ver $xilinx_src/simprims/X_DCM_SP.v
vlog -work simprims_ver $xilinx_src/simprims/X_DSP48.v
vlog -work simprims_ver $xilinx_src/simprims/X_DSP48E.v
vlog -work simprims_ver $xilinx_src/simprims/X_EMAC.v
vlog -work simprims_ver $xilinx_src/simprims/X_FDD.v
vlog -work simprims_ver $xilinx_src/simprims/X_FDDRCPE.v
vlog -work simprims_ver $xilinx_src/simprims/X_FDDRRSE.v
vlog -work simprims_ver $xilinx_src/simprims/X_FF.v
vlog -work simprims_ver $xilinx_src/simprims/X_FIFO16.v
vlog -work simprims_ver $xilinx_src/simprims/X_FIFO18.v
vlog -work simprims_ver $xilinx_src/simprims/X_FIFO18_36.v
vlog -work simprims_ver $xilinx_src/simprims/X_FIFO36_72_EXP.v
vlog -work simprims_ver $xilinx_src/simprims/X_FIFO36_EXP.v
vlog -work simprims_ver $xilinx_src/simprims/X_GT10.v
vlog -work simprims_ver $xilinx_src/simprims/X_GT11.v
vlog -work simprims_ver $xilinx_src/simprims/X_GT11CLK.v
vlog -work simprims_ver $xilinx_src/simprims/X_GT.v
vlog -work simprims_ver $xilinx_src/simprims/X_IBUFDS.v
vlog -work simprims_ver $xilinx_src/simprims/X_IDDR2.v
vlog -work simprims_ver $xilinx_src/simprims/X_IDDR.v
vlog -work simprims_ver $xilinx_src/simprims/X_IDELAY.v
vlog -work simprims_ver $xilinx_src/simprims/X_IDELAYCTRL.v
vlog -work simprims_ver $xilinx_src/simprims/X_INV.v
vlog -work simprims_ver $xilinx_src/simprims/X_IODELAY.v
vlog -work simprims_ver $xilinx_src/simprims/X_IPAD.v
vlog -work simprims_ver $xilinx_src/simprims/X_ISERDES.v
vlog -work simprims_ver $xilinx_src/simprims/X_ISERDES_NODELAY.v
vlog -work simprims_ver $xilinx_src/simprims/X_KEEPER.v
vlog -work simprims_ver $xilinx_src/simprims/X_LATCH.v
vlog -work simprims_ver $xilinx_src/simprims/X_LATCHE.v
vlog -work simprims_ver $xilinx_src/simprims/X_LUT2.v
vlog -work simprims_ver $xilinx_src/simprims/X_LUT3.v
vlog -work simprims_ver $xilinx_src/simprims/X_LUT4.v
vlog -work simprims_ver $xilinx_src/simprims/X_LUT5.v
vlog -work simprims_ver $xilinx_src/simprims/X_LUT6.v
vlog -work simprims_ver $xilinx_src/simprims/X_LUT7.v
vlog -work simprims_ver $xilinx_src/simprims/X_LUT8.v
vlog -work simprims_ver $xilinx_src/simprims/X_MULT18X18.v
vlog -work simprims_ver $xilinx_src/simprims/X_MULT18X18S.v
vlog -work simprims_ver $xilinx_src/simprims/X_MULT18X18SIO.v
vlog -work simprims_ver $xilinx_src/simprims/X_MUX2.v
vlog -work simprims_ver $xilinx_src/simprims/X_MUXDDR.v
vlog -work simprims_ver $xilinx_src/simprims/X_OBUF.v
vlog -work simprims_ver $xilinx_src/simprims/X_OBUFDS.v
vlog -work simprims_ver $xilinx_src/simprims/X_OBUFT.v
vlog -work simprims_ver $xilinx_src/simprims/X_OBUFTDS.v
vlog -work simprims_ver $xilinx_src/simprims/X_ODDR2.v
vlog -work simprims_ver $xilinx_src/simprims/X_ODDR.v
vlog -work simprims_ver $xilinx_src/simprims/X_ONE.v
vlog -work simprims_ver $xilinx_src/simprims/X_OPAD.v
vlog -work simprims_ver $xilinx_src/simprims/X_OR2.v
vlog -work simprims_ver $xilinx_src/simprims/X_OR3.v
vlog -work simprims_ver $xilinx_src/simprims/X_OR4.v
vlog -work simprims_ver $xilinx_src/simprims/X_OR5.v
vlog -work simprims_ver $xilinx_src/simprims/X_OR6.v
vlog -work simprims_ver $xilinx_src/simprims/X_OR7.v
vlog -work simprims_ver $xilinx_src/simprims/X_OR8.v
vlog -work simprims_ver $xilinx_src/simprims/X_OR9.v
vlog -work simprims_ver $xilinx_src/simprims/X_OR16.v
vlog -work simprims_ver $xilinx_src/simprims/X_OR32.v
vlog -work simprims_ver $xilinx_src/simprims/X_OSERDES.v
vlog -work simprims_ver $xilinx_src/simprims/X_PD.v
vlog -work simprims_ver $xilinx_src/simprims/X_PLL_ADV.v
vlog -work simprims_ver $xilinx_src/simprims/X_PMCD.v
vlog -work simprims_ver $xilinx_src/simprims/X_PPC405.v
vlog -work simprims_ver $xilinx_src/simprims/X_PPC405_ADV.v
vlog -work simprims_ver $xilinx_src/simprims/X_PU.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAM32M.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAM64M.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S1.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S1_S1.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S1_S2.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S1_S4.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S1_S8.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S1_S16.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S2.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S2_S2.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S2_S4.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S2_S8.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S2_S16.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S4.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S4_S4.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S4_S8.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S4_S16.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S8.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S8_S8.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S8_S16.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S16.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB4_S16_S16.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S1.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S1_S1.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S1_S2.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S1_S4.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S1_S9.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S1_S18.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S1_S36.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S2.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S2_S2.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S2_S4.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S2_S9.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S2_S18.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S2_S36.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S4.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S4_S4.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S4_S9.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S4_S18.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S4_S36.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S9.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S9_S9.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S9_S18.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S9_S36.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S18.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S18_S18.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S18_S36.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S36.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB16_S36_S36.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB18.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB18SDP.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB36_EXP.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMB36SDP_EXP.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMD16.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMD32.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMD64.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMD64_ADV.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMD128.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMS16.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMS32.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMS64.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMS64_ADV.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMS128.v
vlog -work simprims_ver $xilinx_src/simprims/X_RAMS256.v
vlog -work simprims_ver $xilinx_src/simprims/X_SFF.v
vlog -work simprims_ver $xilinx_src/simprims/X_SRL16E.v
vlog -work simprims_ver $xilinx_src/simprims/X_SRLC16E.v
vlog -work simprims_ver $xilinx_src/simprims/X_SRLC32E.v
vlog -work simprims_ver $xilinx_src/simprims/X_SUH.v
vlog -work simprims_ver $xilinx_src/simprims/X_SYSMON.v
vlog -work simprims_ver $xilinx_src/simprims/X_TRI.v
vlog -work simprims_ver $xilinx_src/simprims/X_UPAD.v
vlog -work simprims_ver $xilinx_src/simprims/X_XOR2.v
vlog -work simprims_ver $xilinx_src/simprims/X_XOR3.v
vlog -work simprims_ver $xilinx_src/simprims/X_XOR4.v
vlog -work simprims_ver $xilinx_src/simprims/X_XOR5.v
vlog -work simprims_ver $xilinx_src/simprims/X_XOR6.v
vlog -work simprims_ver $xilinx_src/simprims/X_XOR7.v
vlog -work simprims_ver $xilinx_src/simprims/X_XOR8.v
vlog -work simprims_ver $xilinx_src/simprims/X_XOR16.v
vlog -work simprims_ver $xilinx_src/simprims/X_XOR32.v

3. Close Modelsim.
4. Edit C:\Modeltech_6.0\modelsim.ini . add :

simprims_ver = $MODEL_TECH/../simprims_ver

save the C:\Modeltech_6.0\modelsim.ini.

Now your Modelsim is ready to simulate using SIMPRIM library using the following command :

vsim -L simprims_ver work.glbl work.your_testbench

Modelsim and Synopsis example : RISC

A design of SRM processor (Simple RISC Microprocessor).
– Download the documentation here
– Download the design files here

The design files incude the synopsys script.

Path and Define Problem in Modelsim Simulation

For example your design is top.v in the C:/verilog directory. The top.v using file altera.v and xilinx.v which is located in the C:/verilog directory. And your simulation directory located on C:/simulation directory. The top.v contains:

`ifdef TARGET_xilinx
`include “xilinx.v”
`else
`include “altera.v”
`endif

module top.v (
clk,
cen,
wen,
din,
addr,
dout
);

wire..
…..

endmodule

If your command :

vlog ../verilog.v

Error will be produce because modelsim can not read altera.v and xilinx.v (altera.v and xilinx.v are not located in simulation directory). You have to used the following command:

vlog ../verilog.v +incdir+../verilog

Now, the next question is how to define TARGET_xilinx ? You have to used the following command:

vlog ../verilog.v +define+TARGET_xilinx +incdir+../verilog

That’s all folks