Divider Architecture

Parallel Divider Architecture :

Here is the example Verilog divider code : divider.pdf

Serial Divider Architecture :

(click the image to enlarge)
divider.pdf

Integer to String and String Concatenation in VHDL

First, make a library called vsilicon (you can use another name). This library constructed from modelsims textio.vhd. The textio.vhd modified and renamed as textio_vs.vhd in order to avoid library error. The Int_to_string procedure/function in textio.vhd also renamed as Int_to_string_vs in textio_vs.vhd. All constant/subtype/variable also renamed for the similar reason. Here is the textio_vs.vhd.(textio_vs.pdf)

on your modelsim prompt, type:

vlib vsilicon
vcom -93 -work vsilicon ../../lib/vsilicon/sim/TEXTIO_VS.vhd

Put the library on your tesbench/design

library vsilicon;
use vsilicon.TextIO_VS.all;

Now you can call Int_to_string_vs function in your tesbench/design.

Example:

verilog_parameter_interface : process
file WFile: Text;
variable LW: Line;
variable IW: integer;
variable last: integer;
variable SW: string(1 to 22);
variable CW: string(1 to 2);
variable NW: string(1 to 20);
variable first : integer := 1;

begin

if (first = 1) then
File_Open(WFile, “leon3parameters.v”, Write_Mode);

CW := Int_to_string_vs(romwidth);
NW := “`define romwidth “;
SW := NW & CW;
WRITE(LW, SW);
WriteLine(WFile, LW);

CW := Int_to_string_vs(romdepth);
NW := “`define romdepth “;
SW := NW & CW;
WRITE(LW, SW);
WriteLine(WFile, LW);

CW := Int_to_string_vs(sramwidth);
NW := “`define sramwidth “;
SW := NW & CW;
WRITE(LW, SW);
WriteLine(WFile, LW);

CW := Int_to_string_vs(sramdepth);
NW := “`define sramdepth “;
SW := NW & CW;
WRITE(LW, SW);
WriteLine(WFile, LW);

File_Close(WFile);
first := 0;
end if;
wait;
end process;

Design Examples For Xilinx University Program XUP Virtex-II Pro Development System : RS232 Interface

Download Here the ISE Project and files design (rs232 vhdl code etc)

http://www.geocities.com/akhmadm/hdl_design/xup_rs232_vga.zip”

xupv2p_user_guide-ch2.pdf

Design example of Games (VGA) for Altera UP1/UP2 board

This is an incremental design, consist of 5 complexity stage. Learn the design by starting from road-game-01, then you can go to the next design, road-game-02.

1. road-game-01

2. road-game-02

3. road-game-03

4. road-game-04

5. road-game-05

Modelsim and Synopsis example : RISC

A design of SRM processor (Simple RISC Microprocessor).
– Download the documentation here
– Download the design files here

The design files incude the synopsys script.

Interfacing text file in VHDL using readline and writeline

You can use the readline and writeline in VHDL like the readln and writeln in c code. For further information about readline and writeline read the $Modeltech\vhdl_src\std\textio.vhd.

Download here, the example of readline and writeline :

Using Conv_Integer for behavioral memory design in VHDL

If you plan your design will be implemented in FPGA, you have use the syncronous memory. In the simulation phase, you can use the generic behavioral memory design, but in the fpga implementation phase you have change the generic behavioral memory into the vendor memory(Xilinx Core or Altera Megafunction).

Here is the generic behavioral memory code :

Register with scan port


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity reg32sc is
port (
sc_in : in std_logic;
sc_en : in std_logic;
sc_out : out std_logic;
clk : in std_logic;
rst : in std_logic;
ena : in std_logic;
d : in std_logic_vector (31 downto 0);
q : out std_logic_vector (31 downto 0)
);
end reg32sc;

architecture reg32sc_rtl of reg32sc is
signal mem : std_logic_vector (31 downto 0);
signal q_s : std_logic_vector (31 downto 0);
begin

mem

LFSR Testbench

lfsr_dongle.vhd

lfsr_tb.vhd